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arm-trusted-firmware/plat/arm/board/corstone700/platform.mk

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plat/arm: Introduce corstone700 platform. This patch adds support for Corstone-700 foundation IP, which integrates both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible subsystem. This is an example implementation of Corstone-700 IP host firmware. Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as bringing Host out RESET. Host will start execution directly from BL32 and then will jump to Linux. It is an initial port and additional features are expected to be added later. Change-Id: I7b5c0278243d574284b777b2408375d007a7736e Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2018-11-28 11:20:37 +00:00
#
Corstone700: add support for mhuv2 in arm TF-A Note: This patch implements in-band messaging protocol only. ARM has launched a next version of MHU i.e. MHUv2 with its latest subsystems. The main change is that the MHUv2 is now a distributed IP with different peripheral views (registers) for the sender and receiver. Another main difference is that MHUv1 duplex channels are now split into simplex/half duplex in MHUv2. MHUv2 has a configurable number of communication channels. There is a capability register (MSG_NO_CAP) to find out how many channels are available in a system. The register offsets have also changed for STAT, SET & CLEAR registers from 0x0, 0x8 & 0x10 in MHUv1 to 0x0, 0xC & 0x8 in MHUv2 respectively. 0x0 0x4 0x8 0xC 0x1F ------------------------....----- | STAT | | | SET | | | ------------------------....----- Transmit Channel 0x0 0x4 0x8 0xC 0x1F ------------------------....----- | STAT | | CLR | | | | ------------------------....----- Receive Channel The MHU controller can request the receiver to wake-up and once the request is removed, the receiver may go back to sleep, but the MHU itself does not actively put a receiver to sleep. So, in order to wake-up the receiver when the sender wants to send data, the sender has to set ACCESS_REQUEST register first in order to wake-up receiver, state of which can be detected using ACCESS_READY register. ACCESS_REQUEST has an offset of 0xF88 & ACCESS_READY has an offset of 0xF8C and are accessible only on any sender channel. This patch adds necessary changes in a new file required to support the latest MHUv2 controller. This patch also needs an update in DT binding for ARM MHUv2 as we need a second register base (tx base) which would be used as the send channel base. Change-Id: I1455e08b3d88671a191c558790c503eabe07a8e6 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2020-01-29 16:51:42 +00:00
# Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.
plat/arm: Introduce corstone700 platform. This patch adds support for Corstone-700 foundation IP, which integrates both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible subsystem. This is an example implementation of Corstone-700 IP host firmware. Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as bringing Host out RESET. Host will start execution directly from BL32 and then will jump to Linux. It is an initial port and additional features are expected to be added later. Change-Id: I7b5c0278243d574284b777b2408375d007a7736e Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2018-11-28 11:20:37 +00:00
#
# SPDX-License-Identifier: BSD-3-Clause
#
corstone700: splitting the platform support into FVP and FPGA This patch performs the following: - Creating two corstone700 platforms under corstone700 board: fvp and fpga - Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform - The platform can be specified using the TARGET_PLATFORM Makefile variable (possible values are: fvp or fpga) - Allowing to use u-boot by: - Enabling NEED_BL33 option - Fixing non-secure image base: For no preloaded bl33 we want to have the NS base set on shared ram. Setup a memory map region for NS in shared map and set the bl33 address in the area. - Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected platform - Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163 Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2020-07-06 16:15:23 +01:00
# Making sure the corstone700 platform type is specified
ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),)
$(error TARGET_PLATFORM must be fpga or fvp)
endif
plat/arm: Introduce corstone700 platform. This patch adds support for Corstone-700 foundation IP, which integrates both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible subsystem. This is an example implementation of Corstone-700 IP host firmware. Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as bringing Host out RESET. Host will start execution directly from BL32 and then will jump to Linux. It is an initial port and additional features are expected to be added later. Change-Id: I7b5c0278243d574284b777b2408375d007a7736e Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2018-11-28 11:20:37 +00:00
CORSTONE700_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S
BL32_SOURCES += plat/arm/common/aarch32/arm_helpers.S \
plat/arm/common/arm_console.c \
plat/arm/common/arm_common.c \
lib/xlat_tables/aarch32/xlat_tables.c \
lib/xlat_tables/xlat_tables_common.c \
Corstone700: add support for mhuv2 in arm TF-A Note: This patch implements in-band messaging protocol only. ARM has launched a next version of MHU i.e. MHUv2 with its latest subsystems. The main change is that the MHUv2 is now a distributed IP with different peripheral views (registers) for the sender and receiver. Another main difference is that MHUv1 duplex channels are now split into simplex/half duplex in MHUv2. MHUv2 has a configurable number of communication channels. There is a capability register (MSG_NO_CAP) to find out how many channels are available in a system. The register offsets have also changed for STAT, SET & CLEAR registers from 0x0, 0x8 & 0x10 in MHUv1 to 0x0, 0xC & 0x8 in MHUv2 respectively. 0x0 0x4 0x8 0xC 0x1F ------------------------....----- | STAT | | | SET | | | ------------------------....----- Transmit Channel 0x0 0x4 0x8 0xC 0x1F ------------------------....----- | STAT | | CLR | | | | ------------------------....----- Receive Channel The MHU controller can request the receiver to wake-up and once the request is removed, the receiver may go back to sleep, but the MHU itself does not actively put a receiver to sleep. So, in order to wake-up the receiver when the sender wants to send data, the sender has to set ACCESS_REQUEST register first in order to wake-up receiver, state of which can be detected using ACCESS_READY register. ACCESS_REQUEST has an offset of 0xF88 & ACCESS_READY has an offset of 0xF8C and are accessible only on any sender channel. This patch adds necessary changes in a new file required to support the latest MHUv2 controller. This patch also needs an update in DT binding for ARM MHUv2 as we need a second register base (tx base) which would be used as the send channel base. Change-Id: I1455e08b3d88671a191c558790c503eabe07a8e6 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2020-01-29 16:51:42 +00:00
${CORSTONE700_CPU_LIBS} \
corstone700: splitting the platform support into FVP and FPGA This patch performs the following: - Creating two corstone700 platforms under corstone700 board: fvp and fpga - Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform - The platform can be specified using the TARGET_PLATFORM Makefile variable (possible values are: fvp or fpga) - Allowing to use u-boot by: - Enabling NEED_BL33 option - Fixing non-secure image base: For no preloaded bl33 we want to have the NS base set on shared ram. Setup a memory map region for NS in shared map and set the bl33 address in the area. - Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected platform - Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163 Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2020-07-06 16:15:23 +01:00
plat/arm/board/corstone700/common/drivers/mhu/mhu.c
plat/arm: Introduce corstone700 platform. This patch adds support for Corstone-700 foundation IP, which integrates both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible subsystem. This is an example implementation of Corstone-700 IP host firmware. Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as bringing Host out RESET. Host will start execution directly from BL32 and then will jump to Linux. It is an initial port and additional features are expected to be added later. Change-Id: I7b5c0278243d574284b777b2408375d007a7736e Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2018-11-28 11:20:37 +00:00
corstone700: splitting the platform support into FVP and FPGA This patch performs the following: - Creating two corstone700 platforms under corstone700 board: fvp and fpga - Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform - The platform can be specified using the TARGET_PLATFORM Makefile variable (possible values are: fvp or fpga) - Allowing to use u-boot by: - Enabling NEED_BL33 option - Fixing non-secure image base: For no preloaded bl33 we want to have the NS base set on shared ram. Setup a memory map region for NS in shared map and set the bl33 address in the area. - Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected platform - Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163 Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2020-07-06 16:15:23 +01:00
PLAT_INCLUDES := -Iplat/arm/board/corstone700/common/include \
Corstone700: add support for mhuv2 in arm TF-A Note: This patch implements in-band messaging protocol only. ARM has launched a next version of MHU i.e. MHUv2 with its latest subsystems. The main change is that the MHUv2 is now a distributed IP with different peripheral views (registers) for the sender and receiver. Another main difference is that MHUv1 duplex channels are now split into simplex/half duplex in MHUv2. MHUv2 has a configurable number of communication channels. There is a capability register (MSG_NO_CAP) to find out how many channels are available in a system. The register offsets have also changed for STAT, SET & CLEAR registers from 0x0, 0x8 & 0x10 in MHUv1 to 0x0, 0xC & 0x8 in MHUv2 respectively. 0x0 0x4 0x8 0xC 0x1F ------------------------....----- | STAT | | | SET | | | ------------------------....----- Transmit Channel 0x0 0x4 0x8 0xC 0x1F ------------------------....----- | STAT | | CLR | | | | ------------------------....----- Receive Channel The MHU controller can request the receiver to wake-up and once the request is removed, the receiver may go back to sleep, but the MHU itself does not actively put a receiver to sleep. So, in order to wake-up the receiver when the sender wants to send data, the sender has to set ACCESS_REQUEST register first in order to wake-up receiver, state of which can be detected using ACCESS_READY register. ACCESS_REQUEST has an offset of 0xF88 & ACCESS_READY has an offset of 0xF8C and are accessible only on any sender channel. This patch adds necessary changes in a new file required to support the latest MHUv2 controller. This patch also needs an update in DT binding for ARM MHUv2 as we need a second register base (tx base) which would be used as the send channel base. Change-Id: I1455e08b3d88671a191c558790c503eabe07a8e6 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2020-01-29 16:51:42 +00:00
-Iinclude/plat/arm/common \
corstone700: splitting the platform support into FVP and FPGA This patch performs the following: - Creating two corstone700 platforms under corstone700 board: fvp and fpga - Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform - The platform can be specified using the TARGET_PLATFORM Makefile variable (possible values are: fvp or fpga) - Allowing to use u-boot by: - Enabling NEED_BL33 option - Fixing non-secure image base: For no preloaded bl33 we want to have the NS base set on shared ram. Setup a memory map region for NS in shared map and set the bl33 address in the area. - Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected platform - Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163 Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2020-07-06 16:15:23 +01:00
-Iplat/arm/board/corstone700/common/drivers/mhu
plat/arm: Introduce corstone700 platform. This patch adds support for Corstone-700 foundation IP, which integrates both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible subsystem. This is an example implementation of Corstone-700 IP host firmware. Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as bringing Host out RESET. Host will start execution directly from BL32 and then will jump to Linux. It is an initial port and additional features are expected to be added later. Change-Id: I7b5c0278243d574284b777b2408375d007a7736e Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2018-11-28 11:20:37 +00:00
NEED_BL32 := yes
Corstone700: add support for mhuv2 in arm TF-A Note: This patch implements in-band messaging protocol only. ARM has launched a next version of MHU i.e. MHUv2 with its latest subsystems. The main change is that the MHUv2 is now a distributed IP with different peripheral views (registers) for the sender and receiver. Another main difference is that MHUv1 duplex channels are now split into simplex/half duplex in MHUv2. MHUv2 has a configurable number of communication channels. There is a capability register (MSG_NO_CAP) to find out how many channels are available in a system. The register offsets have also changed for STAT, SET & CLEAR registers from 0x0, 0x8 & 0x10 in MHUv1 to 0x0, 0xC & 0x8 in MHUv2 respectively. 0x0 0x4 0x8 0xC 0x1F ------------------------....----- | STAT | | | SET | | | ------------------------....----- Transmit Channel 0x0 0x4 0x8 0xC 0x1F ------------------------....----- | STAT | | CLR | | | | ------------------------....----- Receive Channel The MHU controller can request the receiver to wake-up and once the request is removed, the receiver may go back to sleep, but the MHU itself does not actively put a receiver to sleep. So, in order to wake-up the receiver when the sender wants to send data, the sender has to set ACCESS_REQUEST register first in order to wake-up receiver, state of which can be detected using ACCESS_READY register. ACCESS_REQUEST has an offset of 0xF88 & ACCESS_READY has an offset of 0xF8C and are accessible only on any sender channel. This patch adds necessary changes in a new file required to support the latest MHUv2 controller. This patch also needs an update in DT binding for ARM MHUv2 as we need a second register base (tx base) which would be used as the send channel base. Change-Id: I1455e08b3d88671a191c558790c503eabe07a8e6 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2020-01-29 16:51:42 +00:00
CORSTONE700_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
plat/common/plat_gicv2.c \
plat/arm: Introduce corstone700 platform. This patch adds support for Corstone-700 foundation IP, which integrates both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible subsystem. This is an example implementation of Corstone-700 IP host firmware. Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as bringing Host out RESET. Host will start execution directly from BL32 and then will jump to Linux. It is an initial port and additional features are expected to be added later. Change-Id: I7b5c0278243d574284b777b2408375d007a7736e Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2018-11-28 11:20:37 +00:00
plat/arm/common/arm_gicv2.c
# BL1/BL2 Image not a part of the capsule Image for Corstone700
override NEED_BL1 := no
override NEED_BL2 := no
override NEED_BL2U := no
corstone700: splitting the platform support into FVP and FPGA This patch performs the following: - Creating two corstone700 platforms under corstone700 board: fvp and fpga - Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform - The platform can be specified using the TARGET_PLATFORM Makefile variable (possible values are: fvp or fpga) - Allowing to use u-boot by: - Enabling NEED_BL33 option - Fixing non-secure image base: For no preloaded bl33 we want to have the NS base set on shared ram. Setup a memory map region for NS in shared map and set the bl33 address in the area. - Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected platform - Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163 Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2020-07-06 16:15:23 +01:00
override NEED_BL33 := yes
plat/arm: Introduce corstone700 platform. This patch adds support for Corstone-700 foundation IP, which integrates both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible subsystem. This is an example implementation of Corstone-700 IP host firmware. Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as bringing Host out RESET. Host will start execution directly from BL32 and then will jump to Linux. It is an initial port and additional features are expected to be added later. Change-Id: I7b5c0278243d574284b777b2408375d007a7736e Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2018-11-28 11:20:37 +00:00
#TFA for Corstone700 starts from BL32
override RESET_TO_SP_MIN := 1
#Device tree
corstone700: splitting the platform support into FVP and FPGA This patch performs the following: - Creating two corstone700 platforms under corstone700 board: fvp and fpga - Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform - The platform can be specified using the TARGET_PLATFORM Makefile variable (possible values are: fvp or fpga) - Allowing to use u-boot by: - Enabling NEED_BL33 option - Fixing non-secure image base: For no preloaded bl33 we want to have the NS base set on shared ram. Setup a memory map region for NS in shared map and set the bl33 address in the area. - Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected platform - Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163 Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2020-07-06 16:15:23 +01:00
CORSTONE700_HW_CONFIG_DTS := fdts/corstone700_${TARGET_PLATFORM}.dts
CORSTONE700_HW_CONFIG := ${BUILD_PLAT}/fdts/corstone700_${TARGET_PLATFORM}.dtb
plat/arm: Introduce corstone700 platform. This patch adds support for Corstone-700 foundation IP, which integrates both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible subsystem. This is an example implementation of Corstone-700 IP host firmware. Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as bringing Host out RESET. Host will start execution directly from BL32 and then will jump to Linux. It is an initial port and additional features are expected to be added later. Change-Id: I7b5c0278243d574284b777b2408375d007a7736e Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2018-11-28 11:20:37 +00:00
FDT_SOURCES += ${CORSTONE700_HW_CONFIG_DTS}
$(eval CORSTONE700_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(CORSTONE700_HW_CONFIG_DTS)))
# Add the HW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${CORSTONE700_HW_CONFIG},--hw-config))
# Check for Linux kernel as a BL33 image by default
$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
ifndef ARM_PRELOADED_DTB_BASE
$(error "ARM_PRELOADED_DTB_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.")
endif
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
corstone700: splitting the platform support into FVP and FPGA This patch performs the following: - Creating two corstone700 platforms under corstone700 board: fvp and fpga - Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform - The platform can be specified using the TARGET_PLATFORM Makefile variable (possible values are: fvp or fpga) - Allowing to use u-boot by: - Enabling NEED_BL33 option - Fixing non-secure image base: For no preloaded bl33 we want to have the NS base set on shared ram. Setup a memory map region for NS in shared map and set the bl33 address in the area. - Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected platform - Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163 Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2020-07-06 16:15:23 +01:00
# Adding TARGET_PLATFORM as a GCC define (-D option)
$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM})))
plat/arm: Introduce corstone700 platform. This patch adds support for Corstone-700 foundation IP, which integrates both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible subsystem. This is an example implementation of Corstone-700 IP host firmware. Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as bringing Host out RESET. Host will start execution directly from BL32 and then will jump to Linux. It is an initial port and additional features are expected to be added later. Change-Id: I7b5c0278243d574284b777b2408375d007a7736e Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2018-11-28 11:20:37 +00:00
include plat/arm/board/common/board_common.mk