32 lines
1.0 KiB
C
32 lines
1.0 KiB
C
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __CORTEX_A9_H__
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#define __CORTEX_A9_H__
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/*******************************************************************************
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* Cortex-A9 midr with version/revision set to 0
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******************************************************************************/
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#define CORTEX_A9_MIDR 0x410FC090
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A9_ACTLR_SMP_BIT (1 << 6)
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#define CORTEX_A9_ACTLR_FLZW_BIT (1 << 3)
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/*******************************************************************************
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* CPU Power Control Register
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******************************************************************************/
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#define PCR p15, 0, c15, c0, 0
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#ifndef __ASSEMBLY__
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#include <arch_helpers.h>
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DEFINE_COPROCR_RW_FUNCS(pcr, PCR)
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#endif
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#endif /* __CORTEX_A9_H__ */
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