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FVP: Add support for passing platform's topology to DTS 

This patch adds support for passing FVP platform's topology
configuration to DTS files for compilation, which allows to
build DTBs with correct number of clusters and CPUs.
This removes non-existing clusters/CPUs from the compiled
device tree blob and fixes reported Linux errors when trying
to power on absent CPUs/PEs.
If DTS file is passed using FVP_HW_CONFIG_DTS build option from
the platform's makefile, FVP_CLUSTER_COUNT, FVP_MAX_CPUS_PER_CLUSTER
and FVP_MAX_PE_PER_CPU parameters are used, otherwise CI script will
use the default values from the corresponding DTS file.

Change-Id: Idcb45dc6ad5e3eaea18573aff1a01c9344404ab3
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
This commit is contained in:
Alexei Fedorov 2020-05-13 21:13:57 +01:00
parent 611efd96d8
commit 003faaa59f
15 changed files with 769 additions and 819 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

111
fdts/fvp-base-gicv2-psci-aarch32.dts
View File

@ -4,8 +4,15 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/* Configuration: max 4 clusters with up to 4 CPUs */
/dts-v1/;
#define AFF
#define REG_32
#include "fvp-defs.dtsi"
/memreserve/ 0x80000000 0x00010000;
/ {
@ -42,37 +49,7 @@
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
};
CPU_MAP
idle-states {
entry-method = "arm,psci";
@ -96,77 +73,7 @@
};
};
CPU0:cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU1:cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU2:cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x2>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU3:cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x3>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU4:cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU5:cpu@101 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU6:cpu@102 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x102>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU7:cpu@103 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x103>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPUS
L2_0: l2-cache0 {
compatible = "cache";

110
fdts/fvp-base-gicv2-psci.dts
View File

@ -4,8 +4,14 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/* Configuration: max 4 clusters with up to 4 CPUs */
/dts-v1/;
#define AFF
#include "fvp-defs.dtsi"
/memreserve/ 0x80000000 0x00010000;
/ {
@ -42,37 +48,7 @@
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
};
CPU_MAP
idle-states {
entry-method = "arm,psci";
@ -96,77 +72,7 @@
};
};
CPU0:cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU1:cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU2:cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU3:cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU4:cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU5:cpu@101 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU6:cpu@102 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU7:cpu@103 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPUS
L2_0: l2-cache0 {
compatible = "cache";

37
fdts/fvp-base-gicv3-psci-1t.dts
View File

@ -4,38 +4,11 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/* Configuration: max 4 clusters with up to 4 CPUs with 1 thread per each */
/dts-v1/;
#define AFF 00
#include "fvp-defs.dtsi"
#include "fvp-base-gicv3-psci-common.dtsi"
&CPU0 {
reg = <0x0 0x0>;
};
&CPU1 {
reg = <0x0 0x100>;
};
&CPU2 {
reg = <0x0 0x200>;
};
&CPU3 {
reg = <0x0 0x300>;
};
&CPU4 {
reg = <0x0 0x10000>;
};
&CPU5 {
reg = <0x0 0x10100>;
};
&CPU6 {
reg = <0x0 0x10200>;
};
&CPU7 {
reg = <0x0 0x10300>;
};

38
fdts/fvp-base-gicv3-psci-aarch32-1t.dts
View File

@ -4,38 +4,12 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/* Configuration: max 4 clusters with up to 4 CPUs with 1 thread per each */
/dts-v1/;
#define AFF 00
#define REG_32
#include "fvp-defs.dtsi"
#include "fvp-base-gicv3-psci-aarch32-common.dtsi"
&CPU0 {
reg = <0x0>;
};
&CPU1 {
reg = <0x100>;
};
&CPU2 {
reg = <0x200>;
};
&CPU3 {
reg = <0x300>;
};
&CPU4 {
reg = <0x10000>;
};
&CPU5 {
reg = <0x10100>;
};
&CPU6 {
reg = <0x10200>;
};
&CPU7 {
reg = <0x10300>;
};

104
fdts/fvp-base-gicv3-psci-aarch32-common.dtsi
View File

@ -40,37 +40,7 @@
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
};
CPU_MAP
idle-states {
entry-method = "arm,psci";
@ -94,77 +64,7 @@
};
};
CPU0:cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU1:cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU2:cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x2>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU3:cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x3>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU4:cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU5:cpu@101 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU6:cpu@102 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x102>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU7:cpu@103 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x103>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPUS
L2_0: l2-cache0 {
compatible = "cache";

6
fdts/fvp-base-gicv3-psci-aarch32.dts
View File

@ -4,6 +4,12 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/* Configuration: max 4 clusters with up to 4 CPUs */
/dts-v1/;
#define REG_32
#define AFF
#include "fvp-defs.dtsi"
#include "fvp-base-gicv3-psci-aarch32-common.dtsi"

104
fdts/fvp-base-gicv3-psci-common.dtsi
View File

@ -66,37 +66,7 @@
#address-cells = <2>;
#size-cells = <0>;
CPU_MAP:cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
};
CPU_MAP
idle-states {
entry-method = "arm,psci";
@ -120,77 +90,7 @@
};
};
CPU0:cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU1:cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU2:cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU3:cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU4:cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU5:cpu@101 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU6:cpu@102 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU7:cpu@103 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPUS
L2_0: l2-cache0 {
compatible = "cache";

188
fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
View File

@ -4,185 +4,15 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/* DynamIQ configuration: 1 cluster with up to 8 CPUs with 2 threads per each */
/* Set default value if not passed from platform's makefile */
#ifdef FVP_MAX_PE_PER_CPU
#define PE_PER_CPU FVP_MAX_PE_PER_CPU
#else
#define PE_PER_CPU 2
#endif
/dts-v1/;
#include "fvp-base-gicv3-psci-dynamiq-common.dtsi"
&CPU_MAP {
/delete-node/ cluster0;
cluster0 {
core0 {
thread0 {
cpu = <&CPU0>;
};
thread1 {
cpu = <&CPU1>;
};
};
core1 {
thread0 {
cpu = <&CPU2>;
};
thread1 {
cpu = <&CPU3>;
};
};
core2 {
thread0 {
cpu = <&CPU4>;
};
thread1 {
cpu = <&CPU5>;
};
};
core3 {
thread0 {
cpu = <&CPU6>;
};
thread1 {
cpu = <&CPU7>;
};
};
core4 {
thread0 {
cpu = <&CPU8>;
};
thread1 {
cpu = <&CPU9>;
};
};
core5 {
thread0 {
cpu = <&CPU10>;
};
thread1 {
cpu = <&CPU11>;
};
};
core6 {
thread0 {
cpu = <&CPU12>;
};
thread1 {
cpu = <&CPU13>;
};
};
core7 {
thread0 {
cpu = <&CPU14>;
};
thread1 {
cpu = <&CPU15>;
};
};
};
};
/ {
cpus {
CPU0:cpu@0 {
reg = <0x0 0x0>;
};
CPU1:cpu@1 {
reg = <0x0 0x1>;
};
CPU2:cpu@2 {
reg = <0x0 0x100>;
};
CPU3:cpu@3 {
reg = <0x0 0x101>;
};
CPU4:cpu@100 {
reg = <0x0 0x200>;
};
CPU5:cpu@101 {
reg = <0x0 0x201>;
};
CPU6:cpu@102 {
reg = <0x0 0x300>;
};
CPU7:cpu@103 {
reg = <0x0 0x301>;
};
CPU8:cpu@200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x400>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU9:cpu@201 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x401>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU10:cpu@202 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x500>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU11:cpu@203 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x501>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU12:cpu@300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x600>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU13:cpu@301 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x601>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU14:cpu@302 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x700>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU15:cpu@303 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x701>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
};
};

35
fdts/fvp-base-gicv3-psci-dynamiq-common.dtsi
View File

@ -6,38 +6,5 @@
/dts-v1/;
#include "fvp-defs-dynamiq.dtsi"
#include "fvp-base-gicv3-psci-common.dtsi"
/* DynamIQ based designs have upto 8 CPUs in each cluster */
&CPU_MAP {
/delete-node/ cluster0;
/delete-node/ cluster1;
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
core6 {
cpu = <&CPU6>;
};
core7 {
cpu = <&CPU7>;
};
};
};

41
fdts/fvp-base-gicv3-psci-dynamiq.dts
View File

@ -4,38 +4,15 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/* DynamIQ configuration: 1 cluster with up to 8 CPUs */
/* Set default value if not passed from platform's makefile */
#ifdef FVP_MAX_PE_PER_CPU
#define PE_PER_CPU FVP_MAX_PE_PER_CPU
#else
#define PE_PER_CPU 1
#endif
/dts-v1/;
#include "fvp-base-gicv3-psci-dynamiq-common.dtsi"
&CPU0 {
reg = <0x0 0x0>;
};
&CPU1 {
reg = <0x0 0x100>;
};
&CPU2 {
reg = <0x0 0x200>;
};
&CPU3 {
reg = <0x0 0x300>;
};
&CPU4 {
reg = <0x0 0x400>;
};
&CPU5 {
reg = <0x0 0x500>;
};
&CPU6 {
reg = <0x0 0x600>;
};
&CPU7 {
reg = <0x0 0x700>;
};

5
fdts/fvp-base-gicv3-psci.dts
View File

@ -4,6 +4,11 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/* Configuration: max 4 clusters with up to 4 CPUs */
/dts-v1/;
#define AFF
#include "fvp-defs.dtsi"
#include "fvp-base-gicv3-psci-common.dtsi"

289
fdts/fvp-defs-dynamiq.dtsi Normal file
View File

@ -0,0 +1,289 @@
/*
* Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef FVP_DEFS_DYNAMIQ_DTSI
#define FVP_DEFS_DYNAMIQ_DTSI
/* Set default topology values if not passed from platform's makefile */
#ifdef FVP_CLUSTER_COUNT
#define CLUSTER_COUNT FVP_CLUSTER_COUNT
#else
#define CLUSTER_COUNT 1
#endif
#ifdef FVP_MAX_CPUS_PER_CLUSTER
#define CPUS_PER_CLUSTER FVP_MAX_CPUS_PER_CLUSTER
#else
#define CPUS_PER_CLUSTER 8
#endif
#define CONCAT(x, y) x##y
#define CONC(x, y) CONCAT(x, y)
/*
* n - CPU number
* r - MPID
*/
#define CPU(n, r) \
CPU##n:cpu@r## { \
device_type = "cpu"; \
compatible = "arm,armv8"; \
reg = <0x0 0x##r>; \
enable-method = "psci"; \
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; \
next-level-cache = <&L2_0>; \
};
#if (PE_PER_CPU == 2)
#define THREAD(n) \
thread##n { \
cpu = <&CONC(CPU, __COUNTER__)>; \
};
#define CORE(n) \
core##n { \
THREAD(0) \
THREAD(1) \
};
#else /* PE_PER_CPU == 1 */
#define CORE(n) \
core##n { \
cpu = <&CPU##n>;\
};
#endif /* PE_PER_CORE */
#if (CPUS_PER_CLUSTER == 1)
#if (PE_PER_CPU == 1)
#define CPUS \
CPU(0, 0)
#else
#define CPUS \
CPU(0, 0) \
CPU(1, 1)
#endif
#define CLUSTER(n) \
cluster##n { \
CORE(0) \
};
#elif (CPUS_PER_CLUSTER == 2)
#if (PE_PER_CPU == 1)
#define CPUS \
CPU(0, 0) \
CPU(1, 100)
#else
#define CPUS \
CPU(0, 0) \
CPU(1, 1) \
CPU(2, 100) \
CPU(3, 101)
#endif
#define CLUSTER(n) \
cluster##n { \
CORE(0) \
CORE(1) \
};
#elif (CPUS_PER_CLUSTER == 3)
#if (PE_PER_CPU == 1)
#define CPUS \
CPU(0, 0) \
CPU(1, 100) \
CPU(2, 200)
#else
#define CPUS \
CPU(0, 0) \
CPU(1, 1) \
CPU(2, 100) \
CPU(3, 101) \
CPU(4, 200) \
CPU(5, 201)
#endif
#define CLUSTER(n) \
cluster##n { \
CORE(0) \
CORE(1) \
CORE(2) \
};
#elif (CPUS_PER_CLUSTER == 4)
#if (PE_PER_CPU == 1)
#define CPUS \
CPU(0, 0) \
CPU(1, 100) \
CPU(2, 200) \
CPU(3, 300)
#else
#define CPUS \
CPU(0, 0) \
CPU(1, 1) \
CPU(2, 100) \
CPU(3, 101) \
CPU(4, 200) \
CPU(5, 201) \
CPU(6, 300) \
CPU(7, 301)
#endif
#define CLUSTER(n) \
cluster##n { \
CORE(0) \
CORE(1) \
CORE(2) \
CORE(3) \
};
#elif (CPUS_PER_CLUSTER == 5)
#if (PE_PER_CPU == 1)
#define CPUS \
CPU(0, 0) \
CPU(1, 100) \
CPU(2, 200) \
CPU(3, 300) \
CPU(4, 400)
#else
#define CPUS \
CPU(0, 0) \
CPU(1, 1) \
CPU(2, 100) \
CPU(3, 101) \
CPU(4, 200) \
CPU(5, 201) \
CPU(6, 300) \
CPU(7, 301) \
CPU(8, 400) \
CPU(9, 401)
#endif
#define CLUSTER(n) \
cluster##n { \
CORE(0) \
CORE(1) \
CORE(2) \
CORE(3) \
CORE(4) \
};
#elif (CPUS_PER_CLUSTER == 6)
#if (PE_PER_CPU == 1)
#define CPUS \
CPU(0, 0) \
CPU(1, 100) \
CPU(2, 200) \
CPU(3, 300) \
CPU(4, 400) \
CPU(5, 500)
#else
#define CPUS \
CPU(0, 0) \
CPU(1, 1) \
CPU(2, 100) \
CPU(3, 101) \
CPU(4, 200) \
CPU(5, 201) \
CPU(6, 300) \
CPU(7, 301) \
CPU(8, 400) \
CPU(9, 401) \
CPU(10, 500) \
CPU(11, 501)
#endif
#define CLUSTER(n) \
cluster##n { \
CORE(0) \
CORE(1) \
CORE(2) \
CORE(3) \
CORE(4) \
CORE(5) \
};
#elif (CPUS_PER_CLUSTER == 7)
#if (PE_PER_CPU == 1)
#define CPUS \
CPU(0, 0) \
CPU(1, 100) \
CPU(2, 200) \
CPU(3, 300) \
CPU(4, 400) \
CPU(5, 500) \
CPU(6, 600)
#else
#define CPUS \
CPU(0, 0) \
CPU(1, 1) \
CPU(2, 100) \
CPU(3, 101) \
CPU(4, 200) \
CPU(5, 201) \
CPU(6, 300) \
CPU(7, 301) \
CPU(8, 400) \
CPU(9, 401) \
CPU(10, 500) \
CPU(11, 501) \
CPU(12, 600) \
CPU(13, 601)
#endif
#define CLUSTER(n) \
cluster##n { \
CORE(0) \
CORE(1) \
CORE(2) \
CORE(3) \
CORE(4) \
CORE(5) \
CORE(6) \
};
#else
#if (PE_PER_CPU == 1)
#define CPUS \
CPU(0, 0) \
CPU(1, 100) \
CPU(2, 200) \
CPU(3, 300) \
CPU(4, 400) \
CPU(5, 500) \
CPU(6, 600) \
CPU(7, 700)
#else
#define CPUS \
CPU(0, 0) \
CPU(1, 1) \
CPU(2, 100) \
CPU(3, 101) \
CPU(4, 200) \
CPU(5, 201) \
CPU(6, 300) \
CPU(7, 301) \
CPU(8, 400) \
CPU(9, 401) \
CPU(10, 500) \
CPU(11, 501) \
CPU(12, 600) \
CPU(13, 601) \
CPU(14, 700) \
CPU(15, 701)
#endif
#define CLUSTER(n) \
cluster##n { \
CORE(0) \
CORE(1) \
CORE(2) \
CORE(3) \
CORE(4) \
CORE(5) \
CORE(6) \
CORE(7) \
};
#endif /* CPUS_PER_CLUSTER */
#define CPU_MAP \
cpu-map { \
CLUSTER(0) \
};
#endif /* FVP_DEFS_DYNAMIQ_DTSI */

400
fdts/fvp-defs.dtsi Normal file
View File

@ -0,0 +1,400 @@
/*
* Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef FVP_DEFS_DTSI
#define FVP_DEFS_DTSI
/* Set default topology values if not passed from platform's makefile */
#ifndef CLUSTER_COUNT
#ifdef FVP_CLUSTER_COUNT
#define CLUSTER_COUNT FVP_CLUSTER_COUNT
#else
#define CLUSTER_COUNT 2
#endif
#endif /* CLUSTER_COUNT */
#ifndef CPUS_PER_CLUSTER
#ifdef FVP_MAX_CPUS_PER_CLUSTER
#define CPUS_PER_CLUSTER FVP_MAX_CPUS_PER_CLUSTER
#else
#define CPUS_PER_CLUSTER 4
#endif
#endif /* CPUS_PER_CLUSTER */
/* Get platform's topology */
#define CPUS_COUNT (CLUSTER_COUNT * CPUS_PER_CLUSTER)
#define CONCAT(x, y) x##y
#define CONC(x, y) CONCAT(x, y)
/* CPU's cluster */
#define CLS(n) (n / CPUS_PER_CLUSTER)
/* CPU's position in cluster */
#define POS(n) (n % CPUS_PER_CLUSTER)
#define ADR(n, c, p) \
CPU##n:cpu@CONC(c, CONC(p, AFF)) {
#define PRE \
device_type = "cpu"; \
compatible = "arm,armv8";
#ifdef REG_32
/* 32-bit address */
#define REG(c, p) \
reg = <CONC(0x, CONC(c, CONC(p, AFF)))>;
#else
/* 64-bit address */
#define REG(c, p) \
reg = <0x0 CONC(0x, CONC(c, CONC(p, AFF)))>;
#endif /* REG_32 */
#define POST \
enable-method = "psci"; \
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; \
next-level-cache = <&L2_0>; \
};
#ifdef REG_32
#define CPU_0 \
CPU0:cpu@0 { \
PRE \
reg = <0x0>; \
POST
#else
#define CPU_0 \
CPU0:cpu@0 { \
PRE \
reg = <0x0 0x0>;\
POST
#endif /* REG_32 */
/*
* n - CPU number
*/
#define CPU(n, c, p) \
ADR(n, c, p) \
PRE \
REG(c, p) \
POST
/* 2 CPUs */
#if (CPUS_COUNT > 1)
#if (CLS(1) == 0)
#define c1
#define p1 1
#else
#define c1 10
#define p1 0
#endif
#define CPU_1 CPU(1, c1, p1) /* CPU1: 0.1; 1.0 */
/* 3 CPUs */
#if (CPUS_COUNT > 2)
#if (CLS(2) == 0)
#define c2
#define p2 2
#elif (CLS(2) == 1)
#define c2 10
#define p2 0
#else
#define c2 20
#define p2 0
#endif
#define CPU_2 CPU(2, c2, p2) /* CPU2: 0.2; 1.0; 2.0 */
/* 4 CPUs */
#if (CPUS_COUNT > 3)
#if (CLS(3) == 0)
#define c3
#elif (CLS(3) == 1)
#define c3 10
#else
#define c3 30
#endif
#if (POS(3) == 0)
#define p3 0
#elif (POS(3) == 1)
#define p3 1
#else
#define p3 3
#endif
#define CPU_3 CPU(3, c3, p3) /* CPU3: 0.3; 1.0; 1.1; 3.0 */
/* 6 CPUs */
#if (CPUS_COUNT > 4)
#if (CLS(4) == 1)
#define c4 10
#else
#define c4 20
#endif
#if (POS(4) == 0)
#define p4 0
#else
#define p4 1
#endif
#if (CLS(5) == 1)
#define c5 10
#else
#define c5 20
#endif
#if (POS(5) == 1)
#define p5 1
#else
#define p5 2
#endif
#define CPU_4 CPU(4, c4, p4) /* CPU4: 1.0; 1.1; 2.0 */
#define CPU_5 CPU(5, c5, p5) /* CPU5: 1.1; 1.2; 2.1 */
/* 8 CPUs */
#if (CPUS_COUNT > 6)
#if (CLS(6) == 1)
#define c6 10
#define p6 2
#elif (CLS(6) == 2)
#define c6 20
#define p6 0
#else
#define c6 30
#define p6 0
#endif
#if (CLS(7) == 1)
#define c7 10
#define p7 3
#elif (CLS(7) == 2)
#define c7 20
#define p7 1
#else
#define c7 30
#define p7 1
#endif
#define CPU_6 CPU(6, c6, p6) /* CPU6: 1.2; 2.0; 3.0 */
#define CPU_7 CPU(7, c7, p7) /* CPU7: 1.3; 2.1; 3.1 */
/* 9 CPUs */
#if (CPUS_COUNT > 8)
#if (POS(8) == 0)
#define p8 0
#else
#define p8 2
#endif
#define CPU_8 CPU(8, 20, p8) /* CPU8: 2.0; 2.2 */
/* 12 CPUs */
#if (CPUS_COUNT > 9)
#if (CLS(9) == 2)
#define c9 20
#define p9 1
#else
#define c9 30
#define p9 0
#endif
#if (CLS(10) == 2)
#define c10 20
#define p10 2
#else
#define c10 30
#define p10 1
#endif
#if (CLS(11) == 2)
#define c11 20
#define p11 3
#else
#define c11 30
#define p11 2
#endif
#define CPU_9 CPU(9, c9, p9) /* CPU9: 2.1; 3.0 */
#define CPU_10 CPU(10, c10, p10) /* CPU10: 2.2; 3.1 */
#define CPU_11 CPU(11, c11, p11) /* CPU11: 2.3; 3.2 */
/* 16 CPUs */
#if (CPUS_COUNT > 12)
#define CPU_12 CPU(12, 30, 0) /* CPU12: 3.0 */
#define CPU_13 CPU(13, 30, 1) /* CPU13: 3.1 */
#define CPU_14 CPU(14, 30, 2) /* CPU14: 3.2 */
#define CPU_15 CPU(15, 30, 3) /* CPU15: 3.3 */
#endif /* > 12 */
#endif /* > 9 */
#endif /* > 8 */
#endif /* > 6 */
#endif /* > 4 */
#endif /* > 3 */
#endif /* > 2 */
#endif /* > 1 */
#if (CPUS_COUNT == 1)
#define CPUS \
CPU_0
#elif (CPUS_COUNT == 2)
#define CPUS \
CPU_0 \
CPU_1
#elif (CPUS_COUNT == 3)
#define CPUS \
CPU_0 \
CPU_1 \
CPU_2
#elif (CPUS_COUNT == 4)
#define CPUS \
CPU_0 \
CPU_1 \
CPU_2 \
CPU_3
#elif (CPUS_COUNT == 6)
#define CPUS \
CPU_0 \
CPU_1 \
CPU_2 \
CPU_3 \
CPU_4 \
CPU_5
#elif (CPUS_COUNT == 8)
#define CPUS \
CPU_0 \
CPU_1 \
CPU_2 \
CPU_3 \
CPU_4 \
CPU_5 \
CPU_6 \
CPU_7
#elif (CPUS_COUNT == 9)
#define CPUS \
CPU_0 \
CPU_1 \
CPU_2 \
CPU_3 \
CPU_4 \
CPU_5 \
CPU_6 \
CPU_7 \
CPU_8
#elif (CPUS_COUNT == 12)
#define CPUS \
CPU_0 \
CPU_1 \
CPU_2 \
CPU_3 \
CPU_4 \
CPU_5 \
CPU_6 \
CPU_7 \
CPU_8 \
CPU_9 \
CPU_10 \
CPU_11
#else
#define CPUS \
CPU_0 \
CPU_1 \
CPU_2 \
CPU_3 \
CPU_4 \
CPU_5 \
CPU_6 \
CPU_7 \
CPU_8 \
CPU_9 \
CPU_10 \
CPU_11 \
CPU_12 \
CPU_13 \
CPU_14 \
CPU_15
#endif /* CPUS_COUNT */
#define CORE(n) \
core##n { \
cpu = <&CONC(CPU, __COUNTER__)>; \
};
/* Max 4 CPUs per cluster */
#if (CPUS_PER_CLUSTER == 1)
#define CLUSTER(n) \
cluster##n { \
CORE(0) \
};
#elif (CPUS_PER_CLUSTER == 2)
#define CLUSTER(n) \
cluster##n { \
CORE(0) \
CORE(1) \
};
#elif (CPUS_PER_CLUSTER == 3)
#define CLUSTER(n) \
cluster##n { \
CORE(0) \
CORE(1) \
CORE(2) \
};
#else
#define CLUSTER(n) \
cluster##n { \
CORE(0) \
CORE(1) \
CORE(2) \
CORE(3) \
};
#endif /* CPUS_PER_CLUSTER */
/* Max 4 clusters */
#if (CLUSTER_COUNT == 1)
#define CPU_MAP \
cpu-map { \
CLUSTER(0) \
};
#elif (CLUSTER_COUNT == 2)
#define CPU_MAP \
cpu-map { \
CLUSTER(0) \
CLUSTER(1) \
};
#elif (CLUSTER_COUNT == 3)
#define CPU_MAP \
cpu-map { \
CLUSTER(0) \
CLUSTER(1) \
CLUSTER(2) \
};
#else
#define CPU_MAP \
cpu-map { \
CLUSTER(0) \
CLUSTER(1) \
CLUSTER(2) \
CLUSTER(3) \
};
#endif /* CLUSTER_COUNT */
#endif /* FVP_DEFS_DTSI */

60
fdts/fvp-foundation-gicv2-psci.dts
View File

@ -4,8 +4,15 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/* Configuration: 1 cluster with up to 4 CPUs */
/dts-v1/;
#define AFF
#define CLUSTER_COUNT 1
#include "fvp-defs.dtsi"
/memreserve/ 0x80000000 0x00010000;
/ {
@ -42,22 +49,7 @@
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
};
CPU_MAP
idle-states {
entry-method = "arm,psci";
@ -81,41 +73,7 @@
};
};
CPU0:cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU1:cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU2:cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU3:cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPUS
L2_0: l2-cache0 {
compatible = "cache";

60
fdts/fvp-foundation-gicv3-psci.dts
View File

@ -4,8 +4,15 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/* Configuration: 1 cluster with up to 4 CPUs */
/dts-v1/;
#define AFF
#define CLUSTER_COUNT 1
#include "fvp-defs.dtsi"
/memreserve/ 0x80000000 0x00010000;
/ {
@ -42,22 +49,7 @@
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
};
CPU_MAP
idle-states {
entry-method = "arm,psci";
@ -81,41 +73,7 @@
};
};
CPU0:cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU1:cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU2:cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPU3:cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
CPUS
L2_0: l2-cache0 {
compatible = "cache";