From abb6fee665a303c21f40a26f1466e5273464e290 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Thu, 18 Jul 2019 13:34:09 +0800 Subject: [PATCH 1/2] plat: imx8mm: Add the support for opteed spd on imx8mq/imx8mm Add the basic support for opteed SPD on imx8mq & imx8mm. Signed-off-by: Jacky Bai Change-Id: I6c4855c89dea78d13d172c3d86cf047f829e51ce --- plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c | 12 ++++++++++++ plat/imx/imx8m/imx8mm/include/platform_def.h | 1 - plat/imx/imx8m/imx8mm/platform.mk | 6 ++++++ plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c | 12 ++++++++++++ plat/imx/imx8m/imx8mq/include/platform_def.h | 1 - plat/imx/imx8m/imx8mq/platform.mk | 6 ++++++ 6 files changed, 36 insertions(+), 2 deletions(-) diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c index c3cd0d0cb..4c5f4f0d1 100644 --- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c +++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c @@ -124,6 +124,18 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); +#ifdef SPD_opteed + /* Populate entry point information for BL32 */ + SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = 0; + + /* Pass TEE base and size to bl33 */ + bl33_image_ep_info.args.arg1 = BL32_BASE; + bl33_image_ep_info.args.arg2 = BL32_SIZE; +#endif + bl31_tzc380_setup(); } diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h index de9e3b5c8..fc35dac14 100644 --- a/plat/imx/imx8m/imx8mm/include/platform_def.h +++ b/plat/imx/imx8m/imx8mm/include/platform_def.h @@ -31,7 +31,6 @@ #define BL31_BASE U(0x920000) #define BL31_LIMIT U(0x940000) -#define BL32_BASE U(0xbe000000) /* non-secure uboot base */ #define PLAT_NS_IMAGE_OFFSET U(0x40200000) diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk index 6d32dbba3..c0cb6c2a5 100644 --- a/plat/imx/imx8m/imx8mm/platform.mk +++ b/plat/imx/imx8m/imx8mm/platform.mk @@ -45,3 +45,9 @@ A53_DISABLE_NON_TEMPORAL_HINT := 0 ERRATA_A53_835769 := 1 ERRATA_A53_843419 := 1 ERRATA_A53_855873 := 1 + +BL32_BASE ?= 0xbe000000 +$(eval $(call add_define,BL32_BASE)) + +BL32_SIZE ?= 0x2000000 +$(eval $(call add_define,BL32_SIZE)) diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c index 26a3b364e..a347389a2 100644 --- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c +++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c @@ -146,6 +146,18 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); +#ifdef SPD_opteed + /* Populate entry point information for BL32 */ + SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = 0; + + /* Pass TEE base and size to bl33 */ + bl33_image_ep_info.args.arg1 = BL32_BASE; + bl33_image_ep_info.args.arg2 = BL32_SIZE; +#endif + bl31_tz380_setup(); } diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h index 3c212e378..9aa759fd3 100644 --- a/plat/imx/imx8m/imx8mq/include/platform_def.h +++ b/plat/imx/imx8m/imx8mq/include/platform_def.h @@ -32,7 +32,6 @@ #define BL31_BASE U(0x910000) #define BL31_LIMIT U(0x920000) -#define BL32_BASE U(0xfe000000) /* non-secure uboot base */ #define PLAT_NS_IMAGE_OFFSET U(0x40200000) diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk index 44ce55587..80ebe4062 100644 --- a/plat/imx/imx8m/imx8mq/platform.mk +++ b/plat/imx/imx8m/imx8mq/platform.mk @@ -44,3 +44,9 @@ A53_DISABLE_NON_TEMPORAL_HINT := 0 ERRATA_A53_835769 := 1 ERRATA_A53_843419 := 1 ERRATA_A53_855873 := 1 + +BL32_BASE ?= 0xfe000000 +$(eval $(call add_define,BL32_BASE)) + +BL32_SIZE ?= 0x2000000 +$(eval $(call add_define,BL32_SIZE)) From 67f629e87e4c5b4eec6c32b37cdac635964ef1cf Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Tue, 5 Nov 2019 15:50:26 +0800 Subject: [PATCH 2/2] plat: imx: Correct the SGIs that used for secure interrupt Normally, SGI6 & SGI7 is used by non-secure world, these two SGIs should not be reserved for secure interrupt purpose. On i.MX8M platform, SGI8 is used for secure group0 IPI for DDR DVFS, So update the code to reserve SGI8 for secure world. Change-Id: Ib1ed9786e0a79bb729b120a0d4d791d13b6f048a Signed-off-by: Jacky Bai --- plat/imx/common/plat_imx8_gic.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/plat/imx/common/plat_imx8_gic.c b/plat/imx/common/plat_imx8_gic.c index 3a7dcfec6..afb9d1f1a 100644 --- a/plat/imx/common/plat_imx8_gic.c +++ b/plat/imx/common/plat_imx8_gic.c @@ -20,9 +20,7 @@ uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; static const interrupt_prop_t g01s_interrupt_props[] = { - INTR_PROP_DESC(6, GIC_HIGHEST_SEC_PRIORITY, - INTR_GROUP1S, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(7, GIC_HIGHEST_SEC_PRIORITY, + INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, GIC_INTR_CFG_LEVEL), };