Enable use of FIQs and IRQs as TSP interrupts
On a GICv2 system, interrupts that should be handled in the secure world are typically signalled as FIQs. On a GICv3 system, these interrupts are signalled as IRQs instead. The mechanism for handling both types of interrupts is the same in both cases. This patch enables the TSP to run on a GICv3 system by: 1. adding support for handling IRQs in the exception handling code. 2. removing use of "fiq" in the names of data structures, macros and functions. The build option TSPD_ROUTE_IRQ_TO_EL3 is deprecated and is replaced with a new build flag TSP_NS_INTR_ASYNC_PREEMPT. For compatibility reasons, if the former build flag is defined, it will be used to define the value for the new build flag. The documentation is also updated accordingly. Change-Id: I1807d371f41c3656322dd259340a57649833065e
This commit is contained in:
Soby Mathew
parent
404dba53ef
commit
02446137a4
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@ -177,7 +177,7 @@ func tsp_vector_table
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b tsp_cpu_off_entry
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b tsp_cpu_resume_entry
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b tsp_cpu_suspend_entry
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b tsp_fiq_entry
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b tsp_sel1_intr_entry
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b tsp_system_off_entry
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b tsp_system_reset_entry
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endfunc tsp_vector_table
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@ -325,13 +325,13 @@ func tsp_cpu_suspend_entry
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restore_args_call_smc
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endfunc tsp_cpu_suspend_entry
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/*---------------------------------------------
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/*-------------------------------------------------
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* This entrypoint is used by the TSPD to pass
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* control for handling a pending S-EL1 FIQ.
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* control for handling a pending S-EL1 Interrupt.
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* 'x0' contains a magic number which indicates
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* this. TSPD expects control to be handed back
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* at the end of FIQ processing. This is done
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* through an SMC. The handover agreement is:
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* at the end of interrupt processing. This is
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* done through an SMC. The handover agreement is:
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*
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* 1. PSTATE.DAIF are set upon entry. 'x1' has
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* the ELR_EL3 from the non-secure state.
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@ -343,40 +343,41 @@ endfunc tsp_cpu_suspend_entry
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* 4. TSP can use 'x0-x18' to enable its C
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* runtime.
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* 5. TSP returns to TSPD using an SMC with
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* 'x0' = TSP_HANDLED_S_EL1_FIQ
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* ---------------------------------------------
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* 'x0' = TSP_HANDLED_S_EL1_INTR
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* ------------------------------------------------
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*/
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func tsp_fiq_entry
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func tsp_sel1_intr_entry
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#if DEBUG
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mov x2, #(TSP_HANDLE_FIQ_AND_RETURN & ~0xffff)
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movk x2, #(TSP_HANDLE_FIQ_AND_RETURN & 0xffff)
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mov x2, #(TSP_HANDLE_SEL1_INTR_AND_RETURN & ~0xffff)
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movk x2, #(TSP_HANDLE_SEL1_INTR_AND_RETURN & 0xffff)
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cmp x0, x2
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b.ne tsp_fiq_entry_panic
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b.ne tsp_sel1_int_entry_panic
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#endif
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/*---------------------------------------------
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/*-------------------------------------------------
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* Save any previous context needed to perform
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* an exception return from S-EL1 e.g. context
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* from a previous IRQ. Update statistics and
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* handle the FIQ before returning to the TSPD.
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* from a previous Non secure Interrupt.
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* Update statistics and handle the S-EL1
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* interrupt before returning to the TSPD.
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* IRQ/FIQs are not enabled since that will
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* complicate the implementation. Execution
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* will be transferred back to the normal world
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* in any case. A non-zero return value from the
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* fiq handler is an error.
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* ---------------------------------------------
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* interrupt handler is an error.
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* ------------------------------------------------
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*/
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save_eret_context x2 x3
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bl tsp_update_sync_fiq_stats
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bl tsp_fiq_handler
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cbnz x0, tsp_fiq_entry_panic
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bl tsp_update_sync_sel1_intr_stats
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bl tsp_common_int_handler
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cbnz x0, tsp_sel1_int_entry_panic
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restore_eret_context x2 x3
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mov x0, #(TSP_HANDLED_S_EL1_FIQ & ~0xffff)
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movk x0, #(TSP_HANDLED_S_EL1_FIQ & 0xffff)
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mov x0, #(TSP_HANDLED_S_EL1_INTR & ~0xffff)
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movk x0, #(TSP_HANDLED_S_EL1_INTR & 0xffff)
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smc #0
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tsp_fiq_entry_panic:
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b tsp_fiq_entry_panic
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endfunc tsp_fiq_entry
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tsp_sel1_int_entry_panic:
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b tsp_sel1_int_entry_panic
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endfunc tsp_sel1_intr_entry
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when this
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@ -70,6 +70,28 @@
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add sp, sp, SCRATCH_REG_SIZE
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.endm
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/* ----------------------------------------------------
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* Common TSP interrupt handling routine
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* ----------------------------------------------------
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*/
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.macro handle_tsp_interrupt label
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/* Enable the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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save_caller_regs_and_lr
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bl tsp_common_int_handler
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cbz x0, interrupt_exit_\label
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/*
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* This interrupt was not targetted to S-EL1 so send it to
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* the monitor and wait for execution to resume.
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*/
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smc #0
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interrupt_exit_\label:
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restore_caller_regs_and_lr
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eret
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.endm
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.globl tsp_exceptions
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/* -----------------------------------------------------
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@ -120,36 +142,12 @@ sync_exception_sp_elx:
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.align 7
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irq_sp_elx:
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/* Enable the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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save_caller_regs_and_lr
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/* We just update some statistics in the handler */
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bl tsp_handle_preemption
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/* Hand over control to the normal world to handle the IRQ */
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smc #0
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/* The resume std smc starts from here */
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restore_caller_regs_and_lr
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eret
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handle_tsp_interrupt irq_sp_elx
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check_vector_size irq_sp_elx
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.align 7
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fiq_sp_elx:
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/* Enable the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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save_caller_regs_and_lr
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bl tsp_fiq_handler
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cbz x0, fiq_sp_elx_done
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/*
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* This FIQ was not targetted to S-EL1 so send it to
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* the monitor and wait for execution to resume.
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*/
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smc #0
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fiq_sp_elx_done:
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restore_caller_regs_and_lr
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eret
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handle_tsp_interrupt fiq_sp_elx
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check_vector_size fiq_sp_elx
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.align 7
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@ -31,38 +31,39 @@
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#include <arch_helpers.h>
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#include <assert.h>
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#include <debug.h>
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#include <gic_v2.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <tsp.h>
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#include "tsp_private.h"
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/*******************************************************************************
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* This function updates the TSP statistics for FIQs handled synchronously i.e
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* the ones that have been handed over by the TSPD. It also keeps count of the
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* number of times control was passed back to the TSPD after handling an FIQ.
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* In the future it will be possible that the TSPD hands over an FIQ to the TSP
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* but does not expect it to return execution. This statistic will be useful to
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* distinguish between these two models of synchronous FIQ handling.
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* The 'elr_el3' parameter contains the address of the instruction in normal
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* world where this FIQ was generated.
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* This function updates the TSP statistics for S-EL1 interrupts handled
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* synchronously i.e the ones that have been handed over by the TSPD. It also
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* keeps count of the number of times control was passed back to the TSPD
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* after handling the interrupt. In the future it will be possible that the
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* TSPD hands over an S-EL1 interrupt to the TSP but does not expect it to
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* return execution. This statistic will be useful to distinguish between these
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* two models of synchronous S-EL1 interrupt handling. The 'elr_el3' parameter
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* contains the address of the instruction in normal world where this S-EL1
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* interrupt was generated.
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******************************************************************************/
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void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3)
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void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3)
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{
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uint32_t linear_id = plat_my_core_pos();
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tsp_stats[linear_id].sync_fiq_count++;
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if (type == TSP_HANDLE_FIQ_AND_RETURN)
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tsp_stats[linear_id].sync_fiq_ret_count++;
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tsp_stats[linear_id].sync_sel1_intr_count++;
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if (type == TSP_HANDLE_SEL1_INTR_AND_RETURN)
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tsp_stats[linear_id].sync_sel1_intr_ret_count++;
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#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
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spin_lock(&console_lock);
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VERBOSE("TSP: cpu 0x%lx sync fiq request from 0x%lx\n",
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VERBOSE("TSP: cpu 0x%lx sync s-el1 interrupt request from 0x%lx\n",
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read_mpidr(), elr_el3);
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VERBOSE("TSP: cpu 0x%lx: %d sync fiq requests, %d sync fiq returns\n",
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VERBOSE("TSP: cpu 0x%lx: %d sync s-el1 interrupt requests,"
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" %d sync s-el1 interrupt returns\n",
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read_mpidr(),
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tsp_stats[linear_id].sync_fiq_count,
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tsp_stats[linear_id].sync_fiq_ret_count);
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tsp_stats[linear_id].sync_sel1_intr_count,
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tsp_stats[linear_id].sync_sel1_intr_ret_count);
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spin_unlock(&console_lock);
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#endif
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}
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@ -87,13 +88,13 @@ int32_t tsp_handle_preemption(void)
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}
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/*******************************************************************************
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* TSP FIQ handler called as a part of both synchronous and asynchronous
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* handling of FIQ interrupts. It returns 0 upon successfully handling a S-EL1
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* FIQ and treats all other FIQs as EL3 interrupts. It assumes that the GIC
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* architecture version in v2.0 and the secure physical timer interrupt is the
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* only S-EL1 interrupt that it needs to handle.
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* TSP interrupt handler is called as a part of both synchronous and
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* asynchronous handling of TSP interrupts. Currently the physical timer
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* interrupt is the only S-EL1 interrupt that this handler expects. It returns
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* 0 upon successfully handling the expected interrupt and all other
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* interrupts are treated as normal world or EL3 interrupts.
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******************************************************************************/
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int32_t tsp_fiq_handler(void)
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int32_t tsp_common_int_handler(void)
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{
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uint32_t linear_id = plat_my_core_pos(), id;
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@ -123,13 +124,13 @@ int32_t tsp_fiq_handler(void)
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plat_ic_end_of_interrupt(id);
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/* Update the statistics and print some messages */
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tsp_stats[linear_id].fiq_count++;
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tsp_stats[linear_id].sel1_intr_count++;
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#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
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spin_lock(&console_lock);
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VERBOSE("TSP: cpu 0x%lx handled fiq %d\n",
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VERBOSE("TSP: cpu 0x%lx handled S-EL1 interrupt %d\n",
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read_mpidr(), id);
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VERBOSE("TSP: cpu 0x%lx: %d fiq requests\n",
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read_mpidr(), tsp_stats[linear_id].fiq_count);
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VERBOSE("TSP: cpu 0x%lx: %d S-EL1 requests\n",
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read_mpidr(), tsp_stats[linear_id].sel1_intr_count);
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spin_unlock(&console_lock);
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#endif
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return 0;
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@ -54,11 +54,14 @@
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typedef struct work_statistics {
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uint32_t fiq_count; /* Number of FIQs on this cpu */
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uint32_t sync_fiq_count; /* Number of sync. fiqs on this cpu */
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uint32_t sync_fiq_ret_count; /* Number of fiq returns on this cpu */
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/* Number of s-el1 interrupts on this cpu */
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uint32_t sel1_intr_count;
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/* Number of non s-el1 interrupts on this cpu which preempted TSP */
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uint32_t preempt_intr_count;
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/* Number of sync s-el1 interrupts on this cpu */
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uint32_t sync_sel1_intr_count;
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/* Number of s-el1 interrupts returns on this cpu */
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uint32_t sync_sel1_intr_ret_count;
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uint32_t smc_count; /* Number of returns on this cpu */
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uint32_t eret_count; /* Number of entries on this cpu */
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uint32_t cpu_on_count; /* Number of cpu on requests */
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@ -116,8 +119,8 @@ void tsp_generic_timer_stop(void);
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void tsp_generic_timer_save(void);
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void tsp_generic_timer_restore(void);
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/* FIQ management functions */
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void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3);
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/* S-EL1 interrupt management functions */
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void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3);
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/* Data structure to keep track of TSP statistics */
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@ -399,12 +399,12 @@ requirements mentioned earlier.
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1. It passes control to the Test Secure Payload to perform its
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initialisation. The TSP provides the address of the vector table
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`tsp_vectors` in the SP which also includes the handler for Secure-EL1
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interrupts in the `fiq_entry` field. The TSPD passes control to the TSP at
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interrupts in the `sel1_intr_entry` field. The TSPD passes control to the TSP at
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this address when it receives a Secure-EL1 interrupt.
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The handover agreement between the TSP and the TSPD requires that the TSPD
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masks all interrupts (`PSTATE.DAIF` bits) when it calls
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`tsp_fiq_entry()`. The TSP has to preserve the callee saved general
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`tsp_sel1_intr_entry()`. The TSP has to preserve the callee saved general
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purpose, SP_EL1/Secure-EL0, LR, VFP and system registers. It can use
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`x0-x18` to enable its C runtime.
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@ -514,7 +514,7 @@ runtime firmware is not aware of through its platform port.
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The routing model for Secure-EL1 and non-secure interrupts chosen by the TSP is
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described in Section 2.2.2. It is known to the TSPD service at build time.
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The TSP implements an entrypoint (`tsp_fiq_entry()`) for handling Secure-EL1
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The TSP implements an entrypoint (`tsp_sel1_intr_entry()`) for handling Secure-EL1
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interrupts taken in non-secure state and routed through the TSPD service
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(synchronous handling model). It passes the reference to this entrypoint via
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`tsp_vectors` to the TSPD service.
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@ -700,9 +700,9 @@ takes the following actions upon being invoked.
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3. It saves the system register context for the non-secure state by calling
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`cm_el1_sysregs_context_save(NON_SECURE);`.
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4. It sets the `ELR_EL3` system register to `tsp_fiq_entry` and sets the
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4. It sets the `ELR_EL3` system register to `tsp_sel1_intr_entry` and sets the
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`SPSR_EL3.DAIF` bits in the secure CPU context. It sets `x0` to
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`TSP_HANDLE_FIQ_AND_RETURN`. If the TSP was in the middle of handling a
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`TSP_HANDLE_SEL1_INTR_AND_RETURN`. If the TSP was in the middle of handling a
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standard SMC, then the `ELR_EL3` and `SPSR_EL3` registers in the secure CPU
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context are saved first.
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@ -723,20 +723,20 @@ state.
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The TSP issues an SMC with `TSP_HANDLED_S_EL1_FIQ` as the function identifier to
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The TSP issues an SMC with `TSP_HANDLED_S_EL1_INTR` as the function identifier to
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signal completion of interrupt handling.
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The TSP issues an SMC with `TSP_PREEMPTED` as the function identifier to signal
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generation of a non-secure interrupt in Secure-EL1.
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The TSPD service takes the following actions in `tspd_smc_handler()` function
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upon receiving an SMC with `TSP_HANDLED_S_EL1_FIQ` and `TSP_PREEMPTED` as the
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upon receiving an SMC with `TSP_HANDLED_S_EL1_INTR` and `TSP_PREEMPTED` as the
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function identifiers:
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1. It ensures that the call originated from the secure state otherwise
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execution returns to the non-secure state with `SMC_UNK` in `x0`.
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2. If the function identifier is `TSP_HANDLED_S_EL1_FIQ`, it restores the
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2. If the function identifier is `TSP_HANDLED_S_EL1_INTR`, it restores the
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saved `ELR_EL3` and `SPSR_EL3` system registers back to the secure CPU
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context (see step 4 above) in case the TSP had been preempted by a non
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secure interrupt earlier. It does not save the secure context since the
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@ -811,7 +811,7 @@ state.
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##### 2.3.3.1 Test secure payload behavior
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The TSPD hands control of a Secure-EL1 interrupt to the TSP at the
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`tsp_fiq_entry()`. The TSP handles the interrupt while ensuring that the
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`tsp_sel1_intr_entry()`. The TSP handles the interrupt while ensuring that the
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handover agreement described in Section 2.2.2.1 is maintained. It updates some
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statistics by calling `tsp_update_sync_fiq_stats()`. It then calls
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`tsp_fiq_handler()` which.
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@ -827,7 +827,7 @@ statistics by calling `tsp_update_sync_fiq_stats()`. It then calls
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end of interrupt processing.
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The TSP passes control back to the TSPD by issuing an SMC64 with
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`TSP_HANDLED_S_EL1_FIQ` as the function identifier.
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`TSP_HANDLED_S_EL1_INTR` as the function identifier.
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The TSP handles interrupts under the asynchronous model as follows.
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@ -278,10 +278,13 @@ performed.
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(Coherent memory region is included) or 0 (Coherent memory region is
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excluded). Default is 1.
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* `TSPD_ROUTE_IRQ_TO_EL3`: A non zero value enables the routing model
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for non-secure interrupts in which they are routed to EL3 (TSPD). The
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default model (when the value is 0) is to route non-secure interrupts
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to S-EL1 (TSP).
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* `TSP_NS_INTR_ASYNC_PREEMPT`: A non zero value enables the interrupt
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routing model which routes non-secure interrupts asynchronously from TSP
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to EL3 causing immediate preemption of TSP. The EL3 is responsible
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for saving and restoring the TSP context in this routing model. The
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default routing model (when the value is 0) is to route non-secure
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interrupts to TSP allowing it to save its context and hand over
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synchronously to EL3 via an SMC.
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* `TRUSTED_BOARD_BOOT`: Boolean flag to include support for the Trusted Board
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Boot feature. When set to '1', BL1 and BL2 images include support to load
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@ -45,11 +45,12 @@
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|||
#define TSP_SYSTEM_RESET_DONE 0xf2000009
|
||||
|
||||
/*
|
||||
* Function identifiers to handle FIQs through the synchronous handling model.
|
||||
* If the TSP was previously interrupted then control has to be returned to
|
||||
* the TSPD after handling the interrupt else execution can remain in the TSP.
|
||||
* Function identifiers to handle S-El1 interrupt through the synchronous
|
||||
* handling model. If the TSP was previously interrupted then control has to
|
||||
* be returned to the TSPD after handling the interrupt else execution can
|
||||
* remain in the TSP.
|
||||
*/
|
||||
#define TSP_HANDLED_S_EL1_FIQ 0xf2000006
|
||||
#define TSP_HANDLED_S_EL1_INTR 0xf2000006
|
||||
|
||||
/* SMC function ID that TSP uses to request service from secure monitor */
|
||||
#define TSP_GET_ARGS 0xf2001000
|
||||
|
|
@ -62,7 +63,7 @@
|
|||
#define TSP_SUB 0x2001
|
||||
#define TSP_MUL 0x2002
|
||||
#define TSP_DIV 0x2003
|
||||
#define TSP_HANDLE_FIQ_AND_RETURN 0x2004
|
||||
#define TSP_HANDLE_SEL1_INTR_AND_RETURN 0x2004
|
||||
|
||||
/*
|
||||
* Generate function IDs for TSP services to be used in SMC calls, by
|
||||
|
|
@ -114,7 +115,7 @@ typedef struct tsp_vectors {
|
|||
tsp_vector_isn_t cpu_off_entry;
|
||||
tsp_vector_isn_t cpu_resume_entry;
|
||||
tsp_vector_isn_t cpu_suspend_entry;
|
||||
tsp_vector_isn_t fiq_entry;
|
||||
tsp_vector_isn_t sel1_intr_entry;
|
||||
tsp_vector_isn_t system_off_entry;
|
||||
tsp_vector_isn_t system_reset_entry;
|
||||
} tsp_vectors_t;
|
||||
|
|
|
|||
|
|
@ -55,7 +55,17 @@ NEED_BL32 := yes
|
|||
|
||||
# Flag used to enable routing of non-secure interrupts to EL3 when they are
|
||||
# generated while the code is executing in S-EL1/0.
|
||||
TSPD_ROUTE_IRQ_TO_EL3 := 0
|
||||
TSP_NS_INTR_ASYNC_PREEMPT := 0
|
||||
|
||||
$(eval $(call assert_boolean,TSPD_ROUTE_IRQ_TO_EL3))
|
||||
$(eval $(call add_define,TSPD_ROUTE_IRQ_TO_EL3))
|
||||
# If TSPD_ROUTE_IRQ_TO_EL3 build flag is defined, use it to define value for
|
||||
# TSP_NS_INTR_ASYNC_PREEMPT for backward compatibility.
|
||||
ifdef TSPD_ROUTE_IRQ_TO_EL3
|
||||
ifeq (${ERROR_DEPRECATED},1)
|
||||
$(error "TSPD_ROUTE_IRQ_TO_EL3 is deprecated. Please use the new build flag TSP_NS_INTR_ASYNC_PREEMPT")
|
||||
endif
|
||||
$(warning "TSPD_ROUTE_IRQ_TO_EL3 is deprecated. Please use the new build flag TSP_NS_INTR_ASYNC_PREEMPT")
|
||||
TSP_NS_INTR_ASYNC_PREEMPT := ${TSPD_ROUTE_IRQ_TO_EL3}
|
||||
endif
|
||||
|
||||
$(eval $(call assert_boolean,TSP_NS_INTR_ASYNC_PREEMPT))
|
||||
$(eval $(call add_define,TSP_NS_INTR_ASYNC_PREEMPT))
|
||||
|
|
|
|||
|
|
@ -108,7 +108,7 @@ uint64_t tspd_handle_sp_preemption(void *handle)
|
|||
/*******************************************************************************
|
||||
* This function is the handler registered for S-EL1 interrupts by the TSPD. It
|
||||
* validates the interrupt and upon success arranges entry into the TSP at
|
||||
* 'tsp_fiq_entry()' for handling the interrupt.
|
||||
* 'tsp_sel1_intr_entry()' for handling the interrupt.
|
||||
******************************************************************************/
|
||||
static uint64_t tspd_sel1_interrupt_handler(uint32_t id,
|
||||
uint32_t flags,
|
||||
|
|
@ -136,44 +136,44 @@ static uint64_t tspd_sel1_interrupt_handler(uint32_t id,
|
|||
* Determine if the TSP was previously preempted. Its last known
|
||||
* context has to be preserved in this case.
|
||||
* The TSP should return control to the TSPD after handling this
|
||||
* FIQ. Preserve essential EL3 context to allow entry into the
|
||||
* TSP at the FIQ entry point using the 'cpu_context' structure.
|
||||
* There is no need to save the secure system register context
|
||||
* since the TSP is supposed to preserve it during S-EL1 interrupt
|
||||
* handling.
|
||||
* S-EL1 interrupt. Preserve essential EL3 context to allow entry into
|
||||
* the TSP at the S-EL1 interrupt entry point using the 'cpu_context'
|
||||
* structure. There is no need to save the secure system register
|
||||
* context since the TSP is supposed to preserve it during S-EL1
|
||||
* interrupt handling.
|
||||
*/
|
||||
if (get_std_smc_active_flag(tsp_ctx->state)) {
|
||||
tsp_ctx->saved_spsr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx,
|
||||
CTX_SPSR_EL3);
|
||||
tsp_ctx->saved_elr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx,
|
||||
CTX_ELR_EL3);
|
||||
#if TSPD_ROUTE_IRQ_TO_EL3
|
||||
#if TSP_NS_INTR_ASYNC_PREEMPT
|
||||
/*Need to save the previously interrupted secure context */
|
||||
memcpy(&tsp_ctx->sp_ctx, &tsp_ctx->cpu_ctx, TSPD_SP_CTX_SIZE);
|
||||
#endif
|
||||
}
|
||||
|
||||
cm_el1_sysregs_context_restore(SECURE);
|
||||
cm_set_elr_spsr_el3(SECURE, (uint64_t) &tsp_vectors->fiq_entry,
|
||||
cm_set_elr_spsr_el3(SECURE, (uint64_t) &tsp_vectors->sel1_intr_entry,
|
||||
SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS));
|
||||
|
||||
cm_set_next_eret_context(SECURE);
|
||||
|
||||
/*
|
||||
* Tell the TSP that it has to handle an FIQ synchronously. Also the
|
||||
* instruction in normal world where the interrupt was generated is
|
||||
* passed for debugging purposes. It is safe to retrieve this address
|
||||
* from ELR_EL3 as the secure context will not take effect until
|
||||
* el3_exit().
|
||||
* Tell the TSP that it has to handle a S-EL1 interrupt synchronously.
|
||||
* Also the instruction in normal world where the interrupt was
|
||||
* generated is passed for debugging purposes. It is safe to retrieve
|
||||
* this address from ELR_EL3 as the secure context will not take effect
|
||||
* until el3_exit().
|
||||
*/
|
||||
SMC_RET2(&tsp_ctx->cpu_ctx, TSP_HANDLE_FIQ_AND_RETURN, read_elr_el3());
|
||||
SMC_RET2(&tsp_ctx->cpu_ctx, TSP_HANDLE_SEL1_INTR_AND_RETURN, read_elr_el3());
|
||||
}
|
||||
|
||||
#if TSPD_ROUTE_IRQ_TO_EL3
|
||||
#if TSP_NS_INTR_ASYNC_PREEMPT
|
||||
/*******************************************************************************
|
||||
* This function is the handler registered for S-EL1 interrupts by the TSPD. It
|
||||
* validates the interrupt and upon success arranges entry into the TSP at
|
||||
* 'tsp_fiq_entry()' for handling the interrupt.
|
||||
* This function is the handler registered for Non secure interrupts by the
|
||||
* TSPD. It validates the interrupt and upon success arranges entry into the
|
||||
* normal world for handling the interrupt.
|
||||
******************************************************************************/
|
||||
static uint64_t tspd_ns_interrupt_handler(uint32_t id,
|
||||
uint32_t flags,
|
||||
|
|
@ -327,10 +327,10 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
|
|||
|
||||
/*
|
||||
* This function ID is used only by the TSP to indicate that it has
|
||||
* finished handling a S-EL1 FIQ interrupt. Execution should resume
|
||||
* finished handling a S-EL1 interrupt. Execution should resume
|
||||
* in the normal world.
|
||||
*/
|
||||
case TSP_HANDLED_S_EL1_FIQ:
|
||||
case TSP_HANDLED_S_EL1_INTR:
|
||||
if (ns)
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
|
||||
|
|
@ -347,7 +347,7 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
|
|||
SMC_SET_EL3(&tsp_ctx->cpu_ctx,
|
||||
CTX_ELR_EL3,
|
||||
tsp_ctx->saved_elr_el3);
|
||||
#if TSPD_ROUTE_IRQ_TO_EL3
|
||||
#if TSP_NS_INTR_ASYNC_PREEMPT
|
||||
/*
|
||||
* Need to restore the previously interrupted
|
||||
* secure context.
|
||||
|
|
@ -408,7 +408,7 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
|
|||
if (rc)
|
||||
panic();
|
||||
|
||||
#if TSPD_ROUTE_IRQ_TO_EL3
|
||||
#if TSP_NS_INTR_ASYNC_PREEMPT
|
||||
/*
|
||||
* Register an interrupt handler for NS interrupts when
|
||||
* generated during code executing in secure state are
|
||||
|
|
@ -546,7 +546,7 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
|
|||
set_std_smc_active_flag(tsp_ctx->state);
|
||||
cm_set_elr_el3(SECURE, (uint64_t)
|
||||
&tsp_vectors->std_smc_entry);
|
||||
#if TSPD_ROUTE_IRQ_TO_EL3
|
||||
#if TSP_NS_INTR_ASYNC_PREEMPT
|
||||
/*
|
||||
* Enable the routing of NS interrupts to EL3
|
||||
* during STD SMC processing on this core.
|
||||
|
|
@ -577,7 +577,7 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
|
|||
cm_set_next_eret_context(NON_SECURE);
|
||||
if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_STD) {
|
||||
clr_std_smc_active_flag(tsp_ctx->state);
|
||||
#if TSPD_ROUTE_IRQ_TO_EL3
|
||||
#if TSP_NS_INTR_ASYNC_PREEMPT
|
||||
/*
|
||||
* Disable the routing of NS interrupts to EL3
|
||||
* after STD SMC processing is finished on this
|
||||
|
|
@ -620,7 +620,7 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
|
|||
* We are done stashing the non-secure context. Ask the
|
||||
* secure payload to do the work now.
|
||||
*/
|
||||
#if TSPD_ROUTE_IRQ_TO_EL3
|
||||
#if TSP_NS_INTR_ASYNC_PREEMPT
|
||||
/*
|
||||
* Enable the routing of NS interrupts to EL3 during resumption
|
||||
* of STD SMC call on this core.
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@ static void tspd_cpu_on_finish_handler(uint64_t unused)
|
|||
/* Initialise this cpu's secure context */
|
||||
cm_init_my_context(&tsp_on_entrypoint);
|
||||
|
||||
#if TSPD_ROUTE_IRQ_TO_EL3
|
||||
#if TSP_NS_INTR_ASYNC_PREEMPT
|
||||
/*
|
||||
* Disable the NS interrupt locally since it will be enabled globally
|
||||
* within cm_init_my_context.
|
||||
|
|
|
|||
|
|
@ -183,10 +183,10 @@ CASSERT(TSPD_SP_CTX_SIZE == sizeof(sp_ctx_regs_t), \
|
|||
|
||||
/*******************************************************************************
|
||||
* Structure which helps the SPD to maintain the per-cpu state of the SP.
|
||||
* 'saved_spsr_el3' - temporary copy to allow FIQ handling when the TSP has been
|
||||
* preempted.
|
||||
* 'saved_elr_el3' - temporary copy to allow FIQ handling when the TSP has been
|
||||
* preempted.
|
||||
* 'saved_spsr_el3' - temporary copy to allow S-EL1 interrupt handling when
|
||||
* the TSP has been preempted.
|
||||
* 'saved_elr_el3' - temporary copy to allow S-EL1 interrupt handling when
|
||||
* the TSP has been preempted.
|
||||
* 'state' - collection of flags to track SP state e.g. on/off
|
||||
* 'mpidr' - mpidr to associate a context with a cpu
|
||||
* 'c_rt_ctx' - stack address to restore C runtime context from after
|
||||
|
|
@ -207,7 +207,7 @@ typedef struct tsp_context {
|
|||
uint64_t c_rt_ctx;
|
||||
cpu_context_t cpu_ctx;
|
||||
uint64_t saved_tsp_args[TSP_NUM_ARGS];
|
||||
#if TSPD_ROUTE_IRQ_TO_EL3
|
||||
#if TSP_NS_INTR_ASYNC_PREEMPT
|
||||
sp_ctx_regs_t sp_ctx;
|
||||
#endif
|
||||
} tsp_context_t;
|
||||
|
|
|
|||
Loading…
Reference in New Issue