Merge pull request #382 from vikramkanigiri/vk/tf-issues-312
Configure all secure interrupts on ARM platforms
This commit is contained in:
commit
02516ae42d
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@ -347,9 +347,9 @@ level implementation of the generic timer through the memory mapped interface.
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- Disable the legacy interrupt bypass mechanism.
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- Disable the legacy interrupt bypass mechanism.
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- Configure the priority mask register to allow interrupts of all
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- Configure the priority mask register to allow interrupts of all
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priorities to be signaled to the CPU interface.
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priorities to be signaled to the CPU interface.
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- Mark SGIs 8-15, the secure physical timer interrupt (#29) and the
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- Mark SGIs 8-15 and the other secure interrupts on the platform
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trusted watchdog interrupt (#56) as group0 (secure).
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as group0 (secure).
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- Target the trusted watchdog interrupt to CPU0.
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- Target all secure SPIs to CPU0.
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- Enable these group0 interrupts in the GIC distributor.
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- Enable these group0 interrupts in the GIC distributor.
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- Configure all other interrupts as group1 (non-secure).
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- Configure all other interrupts as group1 (non-secure).
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- Enable signaling of group0 interrupts in the GIC distributor.
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- Enable signaling of group0 interrupts in the GIC distributor.
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@ -58,10 +58,9 @@
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/* Interrupt handling constants */
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/* Interrupt handling constants */
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#define CSS_IRQ_MHU 69
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#define CSS_IRQ_MHU 69
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#define CSS_IRQ_GPU_SMMU_0 71
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#define CSS_IRQ_GPU_SMMU_0 71
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#define CSS_IRQ_GPU_SMMU_1 73
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#define CSS_IRQ_ETR_SMMU 75
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#define CSS_IRQ_TZC 80
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#define CSS_IRQ_TZC 80
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#define CSS_IRQ_TZ_WDOG 86
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#define CSS_IRQ_TZ_WDOG 86
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#define CSS_IRQ_SEC_SYS_TIMER 91
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/*
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/*
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* SCP <=> AP boot configuration
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* SCP <=> AP boot configuration
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@ -113,7 +113,6 @@ ARM_CASSERT_MMAP
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#if IMAGE_BL31 || IMAGE_BL32
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#if IMAGE_BL31 || IMAGE_BL32
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/* Array of secure interrupts to be configured by the gic driver */
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/* Array of secure interrupts to be configured by the gic driver */
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const unsigned int irq_sec_array[] = {
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const unsigned int irq_sec_array[] = {
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IRQ_TZ_WDOG,
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ARM_IRQ_SEC_PHY_TIMER,
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ARM_IRQ_SEC_PHY_TIMER,
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ARM_IRQ_SEC_SGI_0,
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ARM_IRQ_SEC_SGI_0,
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ARM_IRQ_SEC_SGI_1,
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ARM_IRQ_SEC_SGI_1,
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@ -122,7 +121,9 @@ const unsigned int irq_sec_array[] = {
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ARM_IRQ_SEC_SGI_4,
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ARM_IRQ_SEC_SGI_4,
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ARM_IRQ_SEC_SGI_5,
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ARM_IRQ_SEC_SGI_5,
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ARM_IRQ_SEC_SGI_6,
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ARM_IRQ_SEC_SGI_6,
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ARM_IRQ_SEC_SGI_7
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ARM_IRQ_SEC_SGI_7,
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FVP_IRQ_TZ_WDOG,
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FVP_IRQ_SEC_SYS_TIMER
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};
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};
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void plat_arm_gic_init(void)
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void plat_arm_gic_init(void)
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@ -115,7 +115,8 @@
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#define BASE_GICH_BASE 0x2c010000
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#define BASE_GICH_BASE 0x2c010000
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#define BASE_GICV_BASE 0x2c02f000
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#define BASE_GICV_BASE 0x2c02f000
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#define IRQ_TZ_WDOG 56
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#define FVP_IRQ_TZ_WDOG 56
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#define FVP_IRQ_SEC_SYS_TIMER 57
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/*******************************************************************************
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/*******************************************************************************
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@ -98,10 +98,17 @@
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#define PLAT_CSS_IRQ_SEC_LIST CSS_IRQ_MHU, \
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#define PLAT_CSS_IRQ_SEC_LIST CSS_IRQ_MHU, \
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CSS_IRQ_GPU_SMMU_0, \
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CSS_IRQ_GPU_SMMU_0, \
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CSS_IRQ_GPU_SMMU_1, \
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CSS_IRQ_ETR_SMMU, \
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CSS_IRQ_TZC, \
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CSS_IRQ_TZC, \
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CSS_IRQ_TZ_WDOG
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CSS_IRQ_TZ_WDOG, \
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CSS_IRQ_SEC_SYS_TIMER, \
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JUNO_IRQ_DMA_SMMU, \
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JUNO_IRQ_HDLCD0_SMMU, \
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JUNO_IRQ_HDLCD1_SMMU, \
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JUNO_IRQ_USB_SMMU, \
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JUNO_IRQ_THIN_LINKS_SMMU, \
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JUNO_IRQ_SEC_I2C, \
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JUNO_IRQ_GPU_SMMU_1, \
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JUNO_IRQ_ETR_SMMU
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/*
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/*
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* Required ARM CSS SoC based platform porting definitions
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* Required ARM CSS SoC based platform porting definitions
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@ -71,5 +71,16 @@
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#define MMU401_SSD_OFFSET 0x4000
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#define MMU401_SSD_OFFSET 0x4000
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#define MMU401_DMA330_BASE 0x7fb00000
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#define MMU401_DMA330_BASE 0x7fb00000
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/*******************************************************************************
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* Interrupt handling constants
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******************************************************************************/
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#define JUNO_IRQ_DMA_SMMU 126
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#define JUNO_IRQ_HDLCD0_SMMU 128
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#define JUNO_IRQ_HDLCD1_SMMU 130
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#define JUNO_IRQ_USB_SMMU 132
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#define JUNO_IRQ_THIN_LINKS_SMMU 134
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#define JUNO_IRQ_SEC_I2C 137
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#define JUNO_IRQ_GPU_SMMU_1 73
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#define JUNO_IRQ_ETR_SMMU 75
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#endif /* __JUNO_DEF_H__ */
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#endif /* __JUNO_DEF_H__ */
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