From 92e870843e9bd654fd1041d66f284c19ca9c0d4f Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Wed, 9 Mar 2022 22:04:00 +0000 Subject: [PATCH 1/2] fix(errata): workaround for Cortex A78 AE erratum 2376748 Cortex A78 AE erratum 2376748 is a Cat B erratum that applies to revisions <= r0p1. It is still open. The erratum states, "A PE executing a PLDW or PRFM PST instruction that lies on a mispredicted branch path might cause a second PE executing a store exclusive to the same cache line address to fail continuously." The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations to other PE caches. There might be a small performance degradation to this workaround for certain workloads that share data. SDEN is available at https://developer.arm.com/documentation/SDEN-1707912 Signed-off-by: Varun Wadekar Change-Id: I93bd392a870d4584f3e12c8e4626dbe5a3a40a4d --- docs/design/cpu-specific-build-macros.rst | 16 +++++--- include/lib/cpus/aarch64/cortex_a78.h | 1 + include/lib/cpus/aarch64/cortex_a78_ae.h | 8 +++- lib/cpus/aarch64/cortex_a78_ae.S | 45 ++++++++++++++++++++++- lib/cpus/cpu-ops.mk | 10 ++++- 5 files changed, 71 insertions(+), 9 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index b7d116832..13b447a17 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -298,13 +298,17 @@ For Cortex-A78, the following errata build flags are defined : For Cortex-A78 AE, the following errata build flags are defined : -- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to Cortex-A78 - AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is - still open. +- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to + Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. + This erratum is still open. -- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to Cortex-A78 - AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is - still open. +- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to + Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This + erratum is still open. + +- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to + Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This + erratum is still open. For Neoverse N1, the following errata build flags are defined : diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h index f3cb39f26..06c27ad35 100644 --- a/include/lib/cpus/aarch64/cortex_a78.h +++ b/include/lib/cpus/aarch64/cortex_a78.h @@ -35,6 +35,7 @@ #define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30) #define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_A78_ACTLR2_EL1_BIT_0 (ULL(1) << 0) #define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1) #define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2) diff --git a/include/lib/cpus/aarch64/cortex_a78_ae.h b/include/lib/cpus/aarch64/cortex_a78_ae.h index 90b6d6ffa..4108af53a 100644 --- a/include/lib/cpus/aarch64/cortex_a78_ae.h +++ b/include/lib/cpus/aarch64/cortex_a78_ae.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, ARM Limited. All rights reserved. - * Copyright (c) 2021, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,4 +21,10 @@ #define CORTEX_A78_AE_CPUECTLR_EL1 CORTEX_A78_CPUECTLR_EL1 #define CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 CORTEX_A78_CPUECTLR_EL1_BIT_8 +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_A78_AE_ACTLR2_EL1 CORTEX_A78_ACTLR2_EL1 +#define CORTEX_A78_AE_ACTLR2_EL1_BIT_0 CORTEX_A78_ACTLR2_EL1_BIT_0 + #endif /* CORTEX_A78_AE_H */ diff --git a/lib/cpus/aarch64/cortex_a78_ae.S b/lib/cpus/aarch64/cortex_a78_ae.S index bf872dfff..45fb0ad6b 100644 --- a/lib/cpus/aarch64/cortex_a78_ae.S +++ b/lib/cpus/aarch64/cortex_a78_ae.S @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, ARM Limited. All rights reserved. - * Copyright (c) 2021, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -104,6 +104,43 @@ func check_errata_1951502 b cpu_rev_var_range endfunc check_errata_1951502 +/* -------------------------------------------------- + * Errata Workaround for A78 AE Erratum 2376748. + * This applies to revisions r0p0 and r0p1 of A78 AE. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a78_ae_2376748_wa + /* Compare x0 against revisions r0p0 - r0p1 */ + mov x17, x30 + bl check_errata_2376748 + cbz x0, 1f + + /* ------------------------------------------------------- + * Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to + * behave like PLD/PRFM LD and not cause invalidations to + * other PE caches. There might be a small performance + * degradation to this workaround for certain workloads + * that share data. + * ------------------------------------------------------- + */ + mrs x0, CORTEX_A78_AE_ACTLR2_EL1 + orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_0 + msr CORTEX_A78_AE_ACTLR2_EL1, x0 + isb +1: + ret x17 +endfunc errata_a78_ae_2376748_wa + +func check_errata_2376748 + /* Applies to revisions r0p0 and r0p1. */ + mov x1, #CPU_REV(0, 0) + mov x2, #CPU_REV(0, 1) + b cpu_rev_var_range +endfunc check_errata_2376748 + func check_errata_cve_2022_23960 #if WORKAROUND_CVE_2022_23960 mov x0, #ERRATA_APPLIES @@ -132,6 +169,11 @@ func cortex_a78_ae_reset_func bl errata_a78_ae_1951502_wa #endif +#if ERRATA_A78_AE_2376748 + mov x0, x18 + bl errata_a78_ae_2376748_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 @@ -197,6 +239,7 @@ func cortex_a78_ae_errata_report */ report_errata ERRATA_A78_AE_1941500, cortex_a78_ae, 1941500 report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502 + report_errata ERRATA_A78_AE_2376748, cortex_a78_ae, 2376748 report_errata WORKAROUND_CVE_2022_23960, cortex_a78_ae, cve_2022_23960 ldp x8, x30, [sp], #16 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index c7630fb93..748724bcf 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1,6 +1,6 @@ # # Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. -# Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved. +# Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -341,6 +341,10 @@ ERRATA_A78_AE_1941500 ?=0 # to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open. ERRATA_A78_AE_1951502 ?=0 +# Flag to apply erratum 2376748 workaround during reset. This erratum applies +# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open. +ERRATA_A78_AE_2376748 ?=0 + # Flag to apply T32 CLREX workaround during reset. This erratum applies # only to r0p0 and r1p0 of the Neoverse N1 cpu. ERRATA_N1_1043202 ?=0 @@ -838,6 +842,10 @@ $(eval $(call add_define,ERRATA_A78_AE_1941500)) $(eval $(call assert_boolean,ERRATA_A78_AE_1951502)) $(eval $(call add_define,ERRATA_A78_AE_1951502)) +# Process ERRATA_A78_AE_2376748 flag +$(eval $(call assert_boolean,ERRATA_A78_AE_2376748)) +$(eval $(call add_define,ERRATA_A78_AE_2376748)) + # Process ERRATA_N1_1043202 flag $(eval $(call assert_boolean,ERRATA_N1_1043202)) $(eval $(call add_define,ERRATA_N1_1043202)) From 3f4d81dfd26649fbcbbbe993a9f0236f5bb07c8a Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Wed, 9 Mar 2022 22:20:32 +0000 Subject: [PATCH 2/2] fix(errata): workaround for Cortex A78 AE erratum 2395408 Cortex A78 AE erratum 2395408 is a Cat B erratum that applies to revisions <= r0p1. It is still open. This erratum states, "A translation table walk that matches an existing L1 prefetch with a read request outstanding on CHI might fold into the prefetch, which might lead to data corruption for a future instruction fetch" This erratum is avoided by setting CPUACTLR2_EL1[40] to 1 to disable folding of demand requests into older prefetches with L2 miss requests outstanding. SDEN is available at https://developer.arm.com/documentation/SDEN-1707912 Signed-off-by: Varun Wadekar Change-Id: Ic17968987ca3c67fa7f64211bcde6dfcb35ed5d6 --- docs/design/cpu-specific-build-macros.rst | 4 +++ include/lib/cpus/aarch64/cortex_a78.h | 1 + include/lib/cpus/aarch64/cortex_a78_ae.h | 1 + lib/cpus/aarch64/cortex_a78_ae.S | 41 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 +++++ 5 files changed, 55 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 13b447a17..af0e76993 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -310,6 +310,10 @@ For Cortex-A78 AE, the following errata build flags are defined : Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is still open. +- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to + Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This + erratum is still open. + For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h index 06c27ad35..31da99e11 100644 --- a/include/lib/cpus/aarch64/cortex_a78.h +++ b/include/lib/cpus/aarch64/cortex_a78.h @@ -38,6 +38,7 @@ #define CORTEX_A78_ACTLR2_EL1_BIT_0 (ULL(1) << 0) #define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1) #define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define CORTEX_A78_ACTLR2_EL1_BIT_40 (ULL(1) << 40) /******************************************************************************* * CPU Activity Monitor Unit register specific definitions. diff --git a/include/lib/cpus/aarch64/cortex_a78_ae.h b/include/lib/cpus/aarch64/cortex_a78_ae.h index 4108af53a..b68ec1e60 100644 --- a/include/lib/cpus/aarch64/cortex_a78_ae.h +++ b/include/lib/cpus/aarch64/cortex_a78_ae.h @@ -26,5 +26,6 @@ ******************************************************************************/ #define CORTEX_A78_AE_ACTLR2_EL1 CORTEX_A78_ACTLR2_EL1 #define CORTEX_A78_AE_ACTLR2_EL1_BIT_0 CORTEX_A78_ACTLR2_EL1_BIT_0 +#define CORTEX_A78_AE_ACTLR2_EL1_BIT_40 CORTEX_A78_ACTLR2_EL1_BIT_40 #endif /* CORTEX_A78_AE_H */ diff --git a/lib/cpus/aarch64/cortex_a78_ae.S b/lib/cpus/aarch64/cortex_a78_ae.S index 45fb0ad6b..27adc381b 100644 --- a/lib/cpus/aarch64/cortex_a78_ae.S +++ b/lib/cpus/aarch64/cortex_a78_ae.S @@ -141,6 +141,41 @@ func check_errata_2376748 b cpu_rev_var_range endfunc check_errata_2376748 +/* -------------------------------------------------- + * Errata Workaround for A78 AE Erratum 2395408. + * This applies to revisions r0p0 and r0p1 of A78 AE. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a78_ae_2395408_wa + /* Compare x0 against revisions r0p0 - r0p1 */ + mov x17, x30 + bl check_errata_2395408 + cbz x0, 1f + + /* -------------------------------------------------------- + * Disable folding of demand requests into older prefetches + * with L2 miss requests outstanding by setting the + * CPUACTLR2_EL1[40] to 1. + * -------------------------------------------------------- + */ + mrs x0, CORTEX_A78_AE_ACTLR2_EL1 + orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_40 + msr CORTEX_A78_AE_ACTLR2_EL1, x0 + isb +1: + ret x17 +endfunc errata_a78_ae_2395408_wa + +func check_errata_2395408 + /* Applies to revisions r0p0 and r0p1. */ + mov x1, #CPU_REV(0, 0) + mov x2, #CPU_REV(0, 1) + b cpu_rev_var_range +endfunc check_errata_2395408 + func check_errata_cve_2022_23960 #if WORKAROUND_CVE_2022_23960 mov x0, #ERRATA_APPLIES @@ -174,6 +209,11 @@ func cortex_a78_ae_reset_func bl errata_a78_ae_2376748_wa #endif +#if ERRATA_A78_AE_2395408 + mov x0, x18 + bl errata_a78_ae_2395408_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 @@ -240,6 +280,7 @@ func cortex_a78_ae_errata_report report_errata ERRATA_A78_AE_1941500, cortex_a78_ae, 1941500 report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502 report_errata ERRATA_A78_AE_2376748, cortex_a78_ae, 2376748 + report_errata ERRATA_A78_AE_2395408, cortex_a78_ae, 2395408 report_errata WORKAROUND_CVE_2022_23960, cortex_a78_ae, cve_2022_23960 ldp x8, x30, [sp], #16 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 748724bcf..8840f8ed5 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -345,6 +345,10 @@ ERRATA_A78_AE_1951502 ?=0 # to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open. ERRATA_A78_AE_2376748 ?=0 +# Flag to apply erratum 2395408 workaround during reset. This erratum applies +# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open. +ERRATA_A78_AE_2395408 ?=0 + # Flag to apply T32 CLREX workaround during reset. This erratum applies # only to r0p0 and r1p0 of the Neoverse N1 cpu. ERRATA_N1_1043202 ?=0 @@ -846,6 +850,10 @@ $(eval $(call add_define,ERRATA_A78_AE_1951502)) $(eval $(call assert_boolean,ERRATA_A78_AE_2376748)) $(eval $(call add_define,ERRATA_A78_AE_2376748)) +# Process ERRATA_A78_AE_2395408 flag +$(eval $(call assert_boolean,ERRATA_A78_AE_2395408)) +$(eval $(call add_define,ERRATA_A78_AE_2395408)) + # Process ERRATA_N1_1043202 flag $(eval $(call assert_boolean,ERRATA_N1_1043202)) $(eval $(call add_define,ERRATA_N1_1043202))