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Merge pull request #1566 from EvanLloyd/non_secure_uart 

ARM Platforms:Enable non-secure access to UART1
This commit is contained in:
Soby Mathew 2018-09-07 16:34:02 +01:00 committed by GitHub
parent b51d4337c3 2431d00f34
commit 03f3632ce6
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 16 additions and 1 deletions
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9
plat/arm/css/common/css_common.mk
View File

@ -85,3 +85,12 @@ endif
# Process CSS_USE_SCMI_SDS_DRIVER flag
$(eval $(call assert_boolean,CSS_USE_SCMI_SDS_DRIVER))
$(eval $(call add_define,CSS_USE_SCMI_SDS_DRIVER))
# Process CSS_NON_SECURE_UART flag
# This undocumented build option is only to enable debug access to the UART
# from non secure code, which is useful on some platforms.
# Default (obviously) is off.
CSS_NON_SECURE_UART := 0
$(eval $(call assert_boolean,CSS_NON_SECURE_UART))
$(eval $(call add_define,CSS_NON_SECURE_UART))

8
plat/arm/soc/common/soc_css_security.c
View File

@ -23,7 +23,7 @@ void soc_css_init_nic400(void)
/*
* Allow non-secure access to some SOC regions, excluding UART1, which
* remains secure.
* remains secure (unless CSS_NON_SECURE_UART is set).
* Note: This is the NIC-400 device on the SOC
*/
mmio_write_32(SOC_CSS_NIC400_BASE +
@ -36,9 +36,15 @@ void soc_css_init_nic400(void)
NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_PL354_SMC), ~0);
mmio_write_32(SOC_CSS_NIC400_BASE +
NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_APB4_BRIDGE), ~0);
#if CSS_NON_SECURE_UART
/* Configure UART for non-secure access */
mmio_write_32(SOC_CSS_NIC400_BASE +
NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE), ~0);
#else
mmio_write_32(SOC_CSS_NIC400_BASE +
NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE),
~SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1);
#endif /* CSS_NON_SECURE_UART */
}