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Remove build option `ASM_ASSERTION` 

The build option `ENABLE_ASSERTIONS` should be used instead. That way
both C and ASM assertions can be enabled or disabled together.

All occurrences of `ASM_ASSERTION` in common code and ARM platforms have
been replaced by `ENABLE_ASSERTIONS`.

ASM_ASSERTION has been removed from the user guide.

Change-Id: I51f1991f11b9b7ff83e787c9a3270c274748ec6f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This commit is contained in:
Antonio Nino Diaz 2017-04-20 09:58:28 +01:00
parent cc8b56322b
commit 044bb2faab
12 changed files with 29 additions and 33 deletions
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7
Makefile
View File

@ -50,10 +50,13 @@ include ${MAKE_HELPERS_DIRECTORY}build_env.mk
# Default values for build configurations, and their dependencies
################################################################################
ifdef ASM_ASSERTION
$(warning ASM_ASSERTION is removed, use ENABLE_ASSERTIONS instead.)
endif
include ${MAKE_HELPERS_DIRECTORY}defaults.mk
# Assertions enabled for DEBUG builds by default
ASM_ASSERTION := ${DEBUG}
ENABLE_ASSERTIONS := ${DEBUG}
ENABLE_PMF := ${ENABLE_RUNTIME_INSTRUMENTATION}
PLAT := ${DEFAULT_PLAT}
@ -440,7 +443,6 @@ endif
# Build options checks
################################################################################
$(eval $(call assert_boolean,ASM_ASSERTION))
$(eval $(call assert_boolean,COLD_BOOT_SINGLE_CPU))
$(eval $(call assert_boolean,CREATE_KEYS))
$(eval $(call assert_boolean,CTX_INCLUDE_AARCH32_REGS))
@ -480,7 +482,6 @@ $(eval $(call add_define,ARM_CCI_PRODUCT_ID))
$(eval $(call add_define,ARM_ARCH_MAJOR))
$(eval $(call add_define,ARM_ARCH_MINOR))
$(eval $(call add_define,ARM_GIC_ARCH))
$(eval $(call add_define,ASM_ASSERTION))
$(eval $(call add_define,COLD_BOOT_SINGLE_CPU))
$(eval $(call add_define,CTX_INCLUDE_AARCH32_REGS))
$(eval $(call add_define,CTX_INCLUDE_FPREGS))

4
common/aarch32/debug.S
View File

@ -90,7 +90,7 @@ func report_exception
no_ret plat_panic_handler
endfunc report_exception
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
.section .rodata.assert_str, "aS"
assert_msg1:
.asciz "ASSERT: File "
@ -155,7 +155,7 @@ dec_print_loop:
#endif /* LOG_LEVEL >= LOG_LEVEL_INFO */
no_ret plat_panic_handler
endfunc asm_assert
#endif
#endif /* ENABLE_ASSERTIONS */
/*
* This function prints a string from address in r4

4
common/aarch64/debug.S
View File

@ -41,7 +41,7 @@
/* The offset to add to get ascii for numerals '0 - 9' */
#define ASCII_OFFSET_NUM 0x30
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
.section .rodata.assert_str, "aS"
assert_msg1:
.asciz "ASSERT: File "
@ -106,7 +106,7 @@ _assert_loop:
#endif /* LOG_LEVEL >= LOG_LEVEL_INFO */
no_ret plat_panic_handler
endfunc asm_assert
#endif
#endif /* ENABLE_ASSERTIONS */
/*
* This function prints a string from address in x4.

5
docs/user-guide.md
View File

@ -203,11 +203,6 @@ performed.
in MPIDR is set and access the bit-fields in MPIDR accordingly. Default
value of this flag is 0.
* `ASM_ASSERTION`: This flag determines whether the assertion checks within
assembly source files are enabled or not. This option defaults to the
value of `DEBUG` - that is, by default this is only enabled for a debug
build of the firmware.
* `BL2`: This is an optional build option which specifies the path to BL2
image for the `fip` target. In this case, the BL2 in the ARM Trusted
Firmware will not be built.

2
include/common/aarch32/el3_common_macros.S
View File

@ -148,7 +148,7 @@
_init_memory, _init_c_runtime, _exception_vectors
/* Make sure we are in Secure Mode */
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
ldcopr r0, SCR
tst r0, #SCR_NS_BIT
ASM_ASSERT(eq)

2
lib/aarch32/misc_helpers.S
View File

@ -162,7 +162,7 @@ endfunc zeromem
* --------------------------------------------------------------------------
*/
func memcpy4
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
orr r3, r0, r1
tst r3, #0x3
ASM_ASSERT(eq)

8
lib/aarch64/misc_helpers.S
View File

@ -215,7 +215,7 @@ func zeromem_dczva
tmp1 .req x4
tmp2 .req x5
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
/*
* Check for M bit (MMU enabled) of the current SCTLR_EL(1|3)
* register value and panic if the MMU is disabled.
@ -228,7 +228,7 @@ func zeromem_dczva
tst tmp1, #SCTLR_M_BIT
ASM_ASSERT(ne)
#endif /* ASM_ASSERTION */
#endif /* ENABLE_ASSERTIONS */
/* stop_address is the address past the last to zero */
add stop_address, cursor, length
@ -247,7 +247,7 @@ func zeromem_dczva
mov tmp2, #(1 << 2)
lsl block_size, tmp2, block_size
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
/*
* Assumes block size is at least 16 bytes to avoid manual realignment
* of the cursor at the end of the DCZVA loop.
@ -444,7 +444,7 @@ endfunc zeromem_dczva
* --------------------------------------------------------------------------
*/
func memcpy16
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
orr x3, x0, x1
tst x3, #0xf
ASM_ASSERT(eq)

6
lib/cpus/aarch32/aem_generic.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -35,7 +35,7 @@
func aem_generic_core_pwr_dwn
/* Assert if cache is enabled */
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq)
@ -51,7 +51,7 @@ endfunc aem_generic_core_pwr_dwn
func aem_generic_cluster_pwr_dwn
/* Assert if cache is enabled */
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq)

6
lib/cpus/aarch32/cortex_a32.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -76,7 +76,7 @@ func cortex_a32_core_pwr_dwn
push {r12, lr}
/* Assert if cache is enabled */
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq)
@ -107,7 +107,7 @@ func cortex_a32_cluster_pwr_dwn
push {r12, lr}
/* Assert if cache is enabled */
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq)

6
lib/cpus/aarch32/cpu_helpers.S
View File

@ -53,7 +53,7 @@ func reset_handler
/* Get the matching cpu_ops pointer (clobbers: r0 - r5) */
bl get_cpu_ops_ptr
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
cmp r0, #0
ASM_ASSERT(ne)
#endif
@ -92,7 +92,7 @@ func prepare_cpu_pwr_dwn
pop {r2, lr}
ldr r0, [r0, #CPU_DATA_CPU_OPS_PTR]
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
cmp r0, #0
ASM_ASSERT(ne)
#endif
@ -118,7 +118,7 @@ func init_cpu_ops
cmp r1, #0
bne 1f
bl get_cpu_ops_ptr
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
cmp r0, #0
ASM_ASSERT(ne)
#endif

6
lib/cpus/aarch64/cpu_helpers.S
View File

@ -55,7 +55,7 @@ func reset_handler
/* Get the matching cpu_ops pointer */
bl get_cpu_ops_ptr
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
cmp x0, #0
ASM_ASSERT(ne)
#endif
@ -94,7 +94,7 @@ func prepare_cpu_pwr_dwn
mrs x1, tpidr_el3
ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR]
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
cmp x0, #0
ASM_ASSERT(ne)
#endif
@ -120,7 +120,7 @@ func init_cpu_ops
cbnz x0, 1f
mov x10, x30
bl get_cpu_ops_ptr
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
cmp x0, #0
ASM_ASSERT(ne)
#endif

6
plat/common/aarch64/platform_mp_stack.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -131,7 +131,7 @@ endfunc platform_set_stack
* -------------------------------------------------------
*/
func_deprecated platform_get_stack
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
mrs x1, mpidr_el1
cmp x0, x1
ASM_ASSERT(eq)
@ -150,7 +150,7 @@ endfunc_deprecated platform_get_stack
* -----------------------------------------------------
*/
func_deprecated platform_set_stack
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
mrs x1, mpidr_el1
cmp x0, x1
ASM_ASSERT(eq)