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Merge "Add Cortex_A78C CPU lib" into integration

This commit is contained in:
Madhukar Pappireddy 2021-04-06 16:52:53 +02:00 committed by TrustedFirmware Code Review
parent 8078b5c5a0 0a144dd4ea
commit 045b209cc2
4 changed files with 93 additions and 2 deletions
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24
include/lib/cpus/aarch64/cortex_a78c.h Normal file
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@ -0,0 +1,24 @@
/*
* Copyright (c) 2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CORTEX_A78C_H
#define CORTEX_A78C_H
#define CORTEX_A78C_MIDR U(0x410FD4B1)
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define CORTEX_A78C_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
#endif /* CORTEX_A78C_H */

65
lib/cpus/aarch64/cortex_a78c.S Normal file
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@ -0,0 +1,65 @@
/*
* Copyright (c) 2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
#include <cortex_a78c.h>
#include <cpu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/
func cortex_a78c_core_pwr_dwn
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
msr CORTEX_A78C_CPUPWRCTLR_EL1, x0
isb
ret
endfunc cortex_a78c_core_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Cortex A78C. Must follow AAPCS.
*/
func cortex_a78c_errata_report
ret
endfunc cortex_a78c_errata_report
#endif
/* ---------------------------------------------
* This function provides cortex_a78c specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
* x8 - x15 having values of registers to be
* reported.
* ---------------------------------------------
*/
.section .rodata.cortex_a78c_regs, "aS"
cortex_a78c_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
func cortex_a78c_cpu_reg_dump
adr x6, cortex_a78c_regs
mrs x8, CORTEX_A78C_CPUECTLR_EL1
ret
endfunc cortex_a78c_cpu_reg_dump
declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \
CPU_NO_RESET_FUNC, \
cortex_a78c_core_pwr_dwn

3
plat/arm/board/arm_fpga/platform.mk
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@ -70,7 +70,8 @@ else
lib/cpus/aarch64/cortex_klein.S \
lib/cpus/aarch64/cortex_matterhorn.S \
lib/cpus/aarch64/cortex_makalu.S \
lib/cpus/aarch64/cortex_makalu_elp.S
lib/cpus/aarch64/cortex_makalu_elp.S \
lib/cpus/aarch64/cortex_a78c.S
# AArch64/AArch32 cores
FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \

3
plat/arm/board/fvp/platform.mk
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@ -136,7 +136,8 @@ else
lib/cpus/aarch64/cortex_makalu.S \
lib/cpus/aarch64/cortex_makalu_elp.S \
lib/cpus/aarch64/cortex_a65.S \
lib/cpus/aarch64/cortex_a65ae.S
lib/cpus/aarch64/cortex_a65ae.S \
lib/cpus/aarch64/cortex_a78c.S
endif
# AArch64/AArch32 cores
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \