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fconf: Clean confused naming between TB_FW and FW_CONFIG 

Cleaned up confused naming between TB_FW and FW_CONFIG.

Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9e9f6e6ca076d38fee0388f97d370431ae067f08
This commit is contained in:
Manish V Badarkhe 2020-05-31 10:17:59 +01:00
parent 243875eaf9
commit 04e06973e1
13 changed files with 42 additions and 42 deletions
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8
drivers/arm/css/scp/css_bom_bootloader.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -51,13 +51,13 @@ typedef struct {
* All CSS platforms load SCP_BL2/SCP_BL2U just below BL2 (this is where BL31
* usually resides except when ARM_BL31_IN_DRAM is
* set). Ensure that SCP_BL2/SCP_BL2U do not overflow into shared RAM and
* the tb_fw_config.
* the fw_config.
*/
CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
CASSERT(SCP_BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_scp_bl2_overflow);
CASSERT(SCP_BL2U_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_scp_bl2u_overflow);
CASSERT(SCP_BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2_overflow);
CASSERT(SCP_BL2U_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2u_overflow);
static void scp_boot_message_start(void)
{

8
include/drivers/arm/css/css_scp.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -40,13 +40,13 @@ int css_scp_boot_ready(void);
/*
* All CSS platforms load SCP_BL2/SCP_BL2U just below BL2 (this is where BL31
* usually resides except when ARM_BL31_IN_DRAM is
* set). Ensure that SCP_BL2/SCP_BL2U do not overflow into tb_fw_config.
* set). Ensure that SCP_BL2/SCP_BL2U do not overflow into fw_config.
*/
CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
CASSERT(SCP_BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_scp_bl2_overflow);
CASSERT(SCP_BL2U_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_scp_bl2u_overflow);
CASSERT(SCP_BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2_overflow);
CASSERT(SCP_BL2U_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2u_overflow);
#endif
#endif /* CSS_SCP_H */

16
include/plat/arm/common/arm_def.h
View File

@ -346,24 +346,24 @@
#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
/*
* To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base
* To enable FW_CONFIG to be loaded by BL1, define the corresponding base
* and limit. Leave enough space of BL2 meminfo.
*/
#define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
#define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U))
#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
#define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U))
/*
* Boot parameters passed from BL2 to BL31/BL32 are stored here
*/
#define ARM_BL2_MEM_DESC_BASE ARM_TB_FW_CONFIG_LIMIT
#define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT
#define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE + \
(PAGE_SIZE / 2U))
/*
* Define limit of firmware configuration memory:
* ARM_TB_FW_CONFIG + ARM_BL2_MEM_DESC memory
* ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
*/
#define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE)
#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE)
/*******************************************************************************
* BL1 specific defines.
@ -461,7 +461,7 @@
* SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding
* the page reserved for fw_configs) to BL32
*/
# define BL32_BASE ARM_FW_CONFIG_LIMIT
# define BL32_BASE ARM_FW_CONFIGS_LIMIT
# define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
# else
/* Put BL32 below BL2 in the Trusted SRAM.*/
@ -505,7 +505,7 @@
# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE
# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE
# define TSP_PROGBITS_LIMIT BL31_BASE
# define BL32_BASE ARM_FW_CONFIG_LIMIT
# define BL32_BASE ARM_FW_CONFIGS_LIMIT
# define BL32_LIMIT BL31_BASE
# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE

4
lib/fconf/fconf.c
View File

@ -24,9 +24,9 @@ void fconf_load_config(void)
.h.version = (uint8_t)VERSION_2,
.h.size = (uint16_t)sizeof(image_info_t),
.h.attr = 0,
.image_base = ARM_TB_FW_CONFIG_BASE,
.image_base = ARM_FW_CONFIG_BASE,
.image_max_size = (uint32_t)
(ARM_TB_FW_CONFIG_LIMIT - ARM_TB_FW_CONFIG_BASE)
(ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE)
};
VERBOSE("FCONF: Loading FW_CONFIG\n");

8
plat/arm/board/a5ds/include/platform_def.h
View File

@ -188,11 +188,11 @@
#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
/*
* To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base
* To enable FW_CONFIG to be loaded by BL1, define the corresponding base
* and limit. Leave enough space of BL2 meminfo.
*/
#define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
#define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE)
#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
#define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE)
/*******************************************************************************
* BL1 specific defines.
@ -220,7 +220,7 @@
#define BL2_LIMIT BL1_RW_BASE
/* Put BL32 below BL2 in NS DRAM.*/
#define ARM_BL2_MEM_DESC_BASE ARM_TB_FW_CONFIG_LIMIT
#define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT
#define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
- PLAT_ARM_MAX_BL32_SIZE)

6
plat/arm/board/corstone700/include/platform_def.h
View File

@ -83,11 +83,11 @@
#define ARM_CACHE_WRITEBACK_SHIFT 6
/*
* To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base
* To enable FW_CONFIG to be loaded by BL1, define the corresponding base
* and limit. Leave enough space for BL2 meminfo.
*/
#define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
#define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U))
#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
#define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U))
/*
* The max number of regions like RO(code), coherent and data required by

8
plat/arm/board/fvp_ve/include/platform_def.h
View File

@ -169,11 +169,11 @@
#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
/*
* To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base
* To enable FW_CONFIG to be loaded by BL1, define the corresponding base
* and limit. Leave enough space of BL2 meminfo.
*/
#define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
#define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE)
#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
#define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE)
/*******************************************************************************
* BL1 specific defines.
@ -204,7 +204,7 @@
/* Put BL32 below BL2 in NS DRAM.*/
#define ARM_BL2_MEM_DESC_BASE ARM_TB_FW_CONFIG_LIMIT
#define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT
#define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
- PLAT_ARM_MAX_BL32_SIZE)

2
plat/arm/board/juno/include/platform_def.h
View File

@ -254,7 +254,7 @@
* BL31 is loaded over the top.
*/
#define PLAT_CSS_MAX_SCP_BL2_SIZE \
((SCP_BL2_LIMIT - ARM_TB_FW_CONFIG_LIMIT) & ~PAGE_SIZE_MASK)
((SCP_BL2_LIMIT - ARM_FW_CONFIG_LIMIT) & ~PAGE_SIZE_MASK)
#define PLAT_CSS_MAX_SCP_BL2U_SIZE PLAT_CSS_MAX_SCP_BL2_SIZE

10
plat/arm/common/arm_bl2_setup.c
View File

@ -26,10 +26,10 @@
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
/*
* Check that BL2_BASE is above ARM_TB_FW_CONFIG_LIMIT. This reserved page is
* Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is
* for `meminfo_t` data structure and fw_configs passed from BL1.
*/
CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak bl2_early_platform_setup2
@ -50,7 +50,7 @@ CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
* in x0. This memory layout is sitting at the base of the free trusted SRAM.
* Copy it to a safe location before its reclaimed by later BL2 functionality.
******************************************************************************/
void arm_bl2_early_platform_setup(uintptr_t tb_fw_config,
void arm_bl2_early_platform_setup(uintptr_t fw_config,
struct meminfo *mem_layout)
{
/* Initialize the console to provide early debug support */
@ -60,8 +60,8 @@ void arm_bl2_early_platform_setup(uintptr_t tb_fw_config,
bl2_tzram_layout = *mem_layout;
/* Fill the properties struct with the info from the config dtb */
if (tb_fw_config != 0U) {
fconf_populate("TB_FW", tb_fw_config);
if (fw_config != 0U) {
fconf_populate("TB_FW", fw_config);
}
/* Initialise the IO layer and register platform IO devices */

4
plat/arm/common/arm_bl31_setup.c
View File

@ -28,10 +28,10 @@ static entry_point_info_t bl33_image_ep_info;
#if !RESET_TO_BL31
/*
* Check that BL31_BASE is above ARM_TB_FW_CONFIG_LIMIT. The reserved page
* Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page
* is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
*/
CASSERT(BL31_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl31_base_overflows);
CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows);
#endif
/* Weak definitions may be overridden in specific ARM standard platform */

4
plat/arm/common/arm_dyn_cfg.c
View File

@ -170,8 +170,8 @@ void arm_bl1_set_bl2_hash(image_desc_t *image_desc)
/*
* BL2 utility function to initialize dynamic configuration specified by
* TB_FW_CONFIG. Populate the bl_mem_params_node_t of other FW_CONFIGs if
* specified in TB_FW_CONFIG.
* FW_CONFIG. Populate the bl_mem_params_node_t of other FW_CONFIGs if
* specified in FW_CONFIG.
*/
void arm_bl2_dyn_cfg_init(void)
{

4
plat/arm/common/sp_min/arm_sp_min_setup.c
View File

@ -29,10 +29,10 @@ static entry_point_info_t bl33_image_ep_info;
MT_MEMORY | MT_RW | MT_SECURE)
/*
* Check that BL32_BASE is above ARM_TB_FW_CONFIG_LIMIT. The reserved page
* Check that BL32_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page
* is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
*/
CASSERT(BL32_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl32_base_overflows);
CASSERT(BL32_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl32_base_overflows);
/*******************************************************************************
* Return a pointer to the 'entry_point_info' structure of the next image for the

2
plat/arm/css/sgm/include/sgm_base_platform_def.h
View File

@ -138,7 +138,7 @@
* BL31 is loaded over the top.
*/
#define PLAT_CSS_MAX_SCP_BL2_SIZE \
((SCP_BL2_LIMIT - ARM_TB_FW_CONFIG_LIMIT) & ~PAGE_SIZE_MASK)
((SCP_BL2_LIMIT - ARM_FW_CONFIG_LIMIT) & ~PAGE_SIZE_MASK)
#define PLAT_CSS_MAX_SCP_BL2U_SIZE PLAT_CSS_MAX_SCP_BL2_SIZE