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ARM plat: change OP-TEE pageable load base 

Changes ARM_OPTEE_PAGEABLE_LOAD_BASE to end of ARM_AP_TZC_DRAM1.
ARM_OPTEE_PAGEABLE_LOAD_SIZE is also increased to 4MB to optimize
translation table usage.

This change makes loading of paged part easier inside OP-TEE OS as the
previous location of ARM_OPTEE_PAGEABLE_LOAD_BASE normally isn't mapped
if paging is enabled.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
This commit is contained in:
Jens Wiklander 2017-08-24 15:39:09 +02:00
parent 5982fa7902
commit 04f72baeac
1 changed files with 11 additions and 9 deletions
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20
include/plat/arm/common/arm_def.h
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@ -97,16 +97,18 @@
#ifdef SPD_opteed
/*
* BL2 needs to map 3.5MB from 512KB offset in TZC_DRAM1 in order to
* load/authenticate the trusted os extra image. The first 512KB of TZC_DRAM1
* are reserved for trusted os (OPTEE). The extra image loading for OPTEE is
* paged image which only include the paging part using virtual memory but
* without "init" data. OPTEE will copy the "init" data (from pager image) to
* the first 512KB of TZC_DRAM, and then copy the extra image behind the "init"
* data.
* BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
* load/authenticate the trusted os extra image. The first 512KB of
* TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
* for OPTEE is paged image which only include the paging part using
* virtual memory but without "init" data. OPTEE will copy the "init" data
* (from pager image) to the first 512KB of TZC_DRAM, and then copy the
* extra image behind the "init" data.
*/
#define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + 0x80000)
#define ARM_OPTEE_PAGEABLE_LOAD_SIZE 0x380000
#define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \
ARM_AP_TZC_DRAM1_SIZE - \
ARM_OPTEE_PAGEABLE_LOAD_SIZE)
#define ARM_OPTEE_PAGEABLE_LOAD_SIZE 0x400000
#define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \
ARM_OPTEE_PAGEABLE_LOAD_BASE, \
ARM_OPTEE_PAGEABLE_LOAD_SIZE, \