Merge "FVP_Base_AEMv8A platform: Fix cache maintenance operations" into integration
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commit
04fb777f99
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@ -112,6 +112,7 @@
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/* CLIDR definitions */
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/* CLIDR definitions */
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#define LOUIS_SHIFT U(21)
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#define LOUIS_SHIFT U(21)
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#define LOC_SHIFT U(24)
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#define LOC_SHIFT U(24)
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#define CTYPE_SHIFT(n) U(3 * (n - 1))
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#define CLIDR_FIELD_WIDTH U(3)
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#define CLIDR_FIELD_WIDTH U(3)
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/* CSSELR definitions */
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/* CSSELR definitions */
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -18,15 +18,43 @@ func aem_generic_core_pwr_dwn
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msr sctlr_el3, x1
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msr sctlr_el3, x1
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isb
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isb
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mov x0, #DCCISW
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/* ---------------------------------------------
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/* ---------------------------------------------
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* Flush L1 cache to PoU.
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* AEM model supports L3 caches in which case L2
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* will be private per core caches and flush
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* from L1 to L2 is not sufficient.
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* ---------------------------------------------
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* ---------------------------------------------
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*/
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*/
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b dcsw_op_louis
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mrs x1, clidr_el1
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endfunc aem_generic_core_pwr_dwn
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/* ---------------------------------------------
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* Check if L3 cache is implemented.
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* ---------------------------------------------
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*/
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tst x1, ((1 << CLIDR_FIELD_WIDTH) - 1) << CTYPE_SHIFT(3)
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/* ---------------------------------------------
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* There is no L3 cache, flush L1 to L2 only.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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b.eq dcsw_op_level1
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mov x18, x30
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/* ---------------------------------------------
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* Flush L1 cache to L2.
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* ---------------------------------------------
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*/
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bl dcsw_op_level1
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mov x30, x18
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/* ---------------------------------------------
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* Flush L2 cache to L3.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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b dcsw_op_level2
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endfunc aem_generic_core_pwr_dwn
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func aem_generic_cluster_pwr_dwn
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func aem_generic_cluster_pwr_dwn
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/* ---------------------------------------------
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/* ---------------------------------------------
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@ -39,7 +67,7 @@ func aem_generic_cluster_pwr_dwn
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isb
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isb
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/* ---------------------------------------------
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/* ---------------------------------------------
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* Flush L1 and L2 caches to PoC.
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* Flush all caches to PoC.
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* ---------------------------------------------
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* ---------------------------------------------
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*/
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*/
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mov x0, #DCCISW
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mov x0, #DCCISW
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