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Aarch64: Add support for FEAT_MTE3 

This patch provides the following changes:
- Adds definition for FEAT_MTE3 value in ID_AA64PFR1_EL1 register
- Enables Memory Tagging Extension for FEAT_MTE3.

Change-Id: I735988575466fdc083892ec12c1aee89b5faa472
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
This commit is contained in:
Alexei Fedorov 2020-12-01 13:22:25 +00:00
parent 91cc872c64
commit 0563ab08e8
2 changed files with 28 additions and 17 deletions
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14
include/arch/aarch64/arch.h
View File

@ -266,9 +266,17 @@
#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
#define MTE_UNIMPLEMENTED ULL(0)
#define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */
#define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */
/* Memory Tagging Extension is not implemented */
#define MTE_UNIMPLEMENTED U(0)
/* FEAT_MTE: MTE instructions accessible at EL0 are implemented */
#define MTE_IMPLEMENTED_EL0 U(1)
/* FEAT_MTE2: Full MTE is implemented */
#define MTE_IMPLEMENTED_ELX U(2)
/*
* FEAT_MTE3: MTE is implemented with support for
* asymmetric Tag Check Fault handling
*/
#define MTE_IMPLEMENTED_ASY U(3)
#define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16)
#define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf)

31
lib/el3_runtime/aarch64/context_mgmt.c
View File

@ -144,30 +144,33 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
#endif /* !CTX_INCLUDE_PAUTH_REGS */
#if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS
/* Get Memory Tagging Extension support level */
unsigned int mte = get_armv8_5_mte_support();
#endif
/*
* Enable MTE support. Support is enabled unilaterally for the normal
* world, and only for the secure world when CTX_INCLUDE_MTE_REGS is
* set.
*/
#if CTX_INCLUDE_MTE_REGS
assert(get_armv8_5_mte_support() == MTE_IMPLEMENTED_ELX);
assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY));
scr_el3 |= SCR_ATA_BIT;
#else
unsigned int mte = get_armv8_5_mte_support();
if (mte == MTE_IMPLEMENTED_EL0) {
/*
* Can enable MTE across both worlds as no MTE registers are
* used
*/
scr_el3 |= SCR_ATA_BIT;
} else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) {
/*
* Can only enable MTE in Non-Secure world without register
* saving
*/
/*
* When MTE is only implemented at EL0, it can be enabled
* across both worlds as no MTE registers are used.
*/
if ((mte == MTE_IMPLEMENTED_EL0) ||
/*
* When MTE is implemented at all ELs, it can be only enabled
* in Non-Secure world without register saving.
*/
(((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)) &&
(security_state == NON_SECURE))) {
scr_el3 |= SCR_ATA_BIT;
}
#endif
#endif /* CTX_INCLUDE_MTE_REGS */
#ifdef IMAGE_BL31
/*