Merge pull request #1632 from Yann-lms/stm32mp1_mmc
Add MMC support for STM32MP1
This commit is contained in:
Soby Mathew
GitHub
commit
0595abceba
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@ -0,0 +1,126 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <debug.h>
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#include <errno.h>
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#include <io_driver.h>
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#include <io_mmc.h>
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#include <io_storage.h>
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#include <mmc.h>
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#include <stm32_sdmmc2.h>
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#include <string.h>
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/* SDMMC device functions */
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static int mmc_dev_open(const uintptr_t init_params, io_dev_info_t **dev_info);
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static int mmc_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
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io_entity_t *entity);
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static int mmc_dev_init(io_dev_info_t *dev_info, const uintptr_t init_params);
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static int mmc_block_seek(io_entity_t *entity, int mode, ssize_t offset);
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static int mmc_block_read(io_entity_t *entity, uintptr_t buffer, size_t length,
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size_t *length_read);
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static int mmc_block_close(io_entity_t *entity);
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static int mmc_dev_close(io_dev_info_t *dev_info);
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static io_type_t device_type_mmc(void);
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static ssize_t seek_offset;
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static const io_dev_connector_t mmc_dev_connector = {
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.dev_open = mmc_dev_open
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};
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static const io_dev_funcs_t mmc_dev_funcs = {
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.type = device_type_mmc,
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.open = mmc_block_open,
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.seek = mmc_block_seek,
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.size = NULL,
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.read = mmc_block_read,
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.write = NULL,
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.close = mmc_block_close,
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.dev_init = mmc_dev_init,
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.dev_close = mmc_dev_close,
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};
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static const io_dev_info_t mmc_dev_info = {
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.funcs = &mmc_dev_funcs,
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.info = 0,
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};
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/* Identify the device type as mmc device */
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static io_type_t device_type_mmc(void)
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{
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return IO_TYPE_MMC;
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}
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/* Open a connection to the mmc device */
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static int mmc_dev_open(const uintptr_t init_params, io_dev_info_t **dev_info)
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{
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assert(dev_info != NULL);
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*dev_info = (io_dev_info_t *)&mmc_dev_info;
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return 0;
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}
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static int mmc_dev_init(io_dev_info_t *dev_info, const uintptr_t init_params)
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{
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return 0;
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}
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/* Close a connection to the mmc device */
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static int mmc_dev_close(io_dev_info_t *dev_info)
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{
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return 0;
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}
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/* Open a file on the mmc device */
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static int mmc_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
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io_entity_t *entity)
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{
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seek_offset = 0;
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return 0;
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}
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/* Seek to a particular file offset on the mmc device */
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static int mmc_block_seek(io_entity_t *entity, int mode, ssize_t offset)
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{
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seek_offset = offset;
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return 0;
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}
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/* Read data from a file on the mmc device */
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static int mmc_block_read(io_entity_t *entity, uintptr_t buffer,
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size_t length, size_t *length_read)
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{
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*length_read = mmc_read_blocks(seek_offset / MMC_BLOCK_SIZE,
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buffer, length);
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if (*length_read != length) {
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return -EIO;
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}
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return 0;
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}
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/* Close a file on the mmc device */
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static int mmc_block_close(io_entity_t *entity)
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{
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return 0;
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}
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/* Register the mmc driver with the IO abstraction */
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int register_io_dev_mmc(const io_dev_connector_t **dev_con)
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{
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int result;
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assert(dev_con != NULL);
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result = io_register_device(&mmc_dev_info);
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if (result == 0) {
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*dev_con = &mmc_dev_connector;
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}
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return result;
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}
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@ -0,0 +1,384 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <boot_api.h>
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#include <debug.h>
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#include <errno.h>
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#include <io_driver.h>
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#include <io_stm32image.h>
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#include <io_storage.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <stdint.h>
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#include <string.h>
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#include <utils.h>
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static uintptr_t backend_dev_handle;
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static uintptr_t backend_image_spec;
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static uint32_t *stm32_img;
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static uint8_t first_lba_buffer[MAX_LBA_SIZE] __aligned(4);
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static struct stm32image_part_info *current_part;
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/* STM32 Image driver functions */
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static int stm32image_dev_open(const uintptr_t init_params,
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io_dev_info_t **dev_info);
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static int stm32image_partition_open(io_dev_info_t *dev_info,
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const uintptr_t spec, io_entity_t *entity);
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static int stm32image_partition_size(io_entity_t *entity, size_t *length);
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static int stm32image_partition_read(io_entity_t *entity, uintptr_t buffer,
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size_t length, size_t *length_read);
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static int stm32image_partition_close(io_entity_t *entity);
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static int stm32image_dev_init(io_dev_info_t *dev_info,
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const uintptr_t init_params);
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static int stm32image_dev_close(io_dev_info_t *dev_info);
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/* Identify the device type as a virtual driver */
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static io_type_t device_type_stm32image(void)
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{
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return IO_TYPE_STM32IMAGE;
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}
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static const io_dev_connector_t stm32image_dev_connector = {
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.dev_open = stm32image_dev_open
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};
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static const io_dev_funcs_t stm32image_dev_funcs = {
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.type = device_type_stm32image,
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.open = stm32image_partition_open,
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.size = stm32image_partition_size,
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.read = stm32image_partition_read,
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.close = stm32image_partition_close,
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.dev_init = stm32image_dev_init,
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.dev_close = stm32image_dev_close,
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};
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static io_dev_info_t stm32image_dev_info = {
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.funcs = &stm32image_dev_funcs,
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.info = (uintptr_t)0,
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};
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static struct stm32image_device_info stm32image_dev;
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static int get_part_idx_by_binary_type(uint32_t binary_type)
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{
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int i;
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for (i = 0; i < STM32_PART_NUM; i++) {
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if (stm32image_dev.part_info[i].binary_type == binary_type) {
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return i;
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}
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}
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return -EINVAL;
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}
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/* Open a connection to the STM32IMAGE device */
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static int stm32image_dev_open(const uintptr_t init_params,
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io_dev_info_t **dev_info)
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{
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int i;
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struct stm32image_device_info *device_info =
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(struct stm32image_device_info *)init_params;
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assert(dev_info != NULL);
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*dev_info = (io_dev_info_t *)&stm32image_dev_info;
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stm32image_dev.device_size = device_info->device_size;
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stm32image_dev.lba_size = device_info->lba_size;
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for (i = 0; i < STM32_PART_NUM; i++) {
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memcpy(stm32image_dev.part_info[i].name,
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device_info->part_info[i].name, MAX_PART_NAME_SIZE);
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stm32image_dev.part_info[i].part_offset =
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device_info->part_info[i].part_offset;
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stm32image_dev.part_info[i].bkp_offset =
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device_info->part_info[i].bkp_offset;
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}
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return 0;
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}
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/* Do some basic package checks */
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static int stm32image_dev_init(io_dev_info_t *dev_info,
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const uintptr_t init_params)
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{
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int result;
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if ((backend_dev_handle != 0U) || (backend_image_spec != 0U)) {
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ERROR("STM32 Image io supports only one session\n");
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return -ENOMEM;
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}
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/* Obtain a reference to the image by querying the platform layer */
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result = plat_get_image_source(STM32_IMAGE_ID, &backend_dev_handle,
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&backend_image_spec);
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if (result != 0) {
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ERROR("STM32 image error (%i)\n", result);
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return -EINVAL;
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}
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return result;
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}
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/* Close a connection to the STM32 Image device */
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static int stm32image_dev_close(io_dev_info_t *dev_info)
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{
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backend_dev_handle = 0U;
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backend_image_spec = 0U;
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stm32_img = NULL;
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return 0;
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}
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/* Open a partition */
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static int stm32image_partition_open(io_dev_info_t *dev_info,
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const uintptr_t spec, io_entity_t *entity)
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{
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const struct stm32image_part_info *partition_spec;
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int idx;
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assert(entity != NULL);
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partition_spec = (struct stm32image_part_info *)spec;
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assert(partition_spec != NULL);
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idx = get_part_idx_by_binary_type(partition_spec->binary_type);
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if ((idx < 0) || (idx > STM32_PART_NUM)) {
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ERROR("Wrong partition index (%d)\n", idx);
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return -EINVAL;
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}
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current_part = &stm32image_dev.part_info[idx];
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stm32_img = (uint32_t *)¤t_part->part_offset;
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return 0;
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}
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/* Return the size of a partition */
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static int stm32image_partition_size(io_entity_t *entity, size_t *length)
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{
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int result;
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uintptr_t backend_handle;
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size_t bytes_read;
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boot_api_image_header_t *header =
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(boot_api_image_header_t *)first_lba_buffer;
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assert(entity != NULL);
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assert(length != NULL);
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/* Attempt to access the image */
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result = io_open(backend_dev_handle, backend_image_spec,
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&backend_handle);
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if (result < 0) {
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ERROR("%s: io_open (%i)\n", __func__, result);
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return result;
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}
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/* Reset magic header value */
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header->magic = 0;
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while (header->magic == 0U) {
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result = io_seek(backend_handle, IO_SEEK_SET, *stm32_img);
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if (result != 0) {
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ERROR("%s: io_seek (%i)\n", __func__, result);
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break;
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}
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result = io_read(backend_handle, (uintptr_t)header,
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MAX_LBA_SIZE, (size_t *)&bytes_read);
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if (result != 0) {
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ERROR("%s: io_read (%i)\n", __func__, result);
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break;
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}
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if ((header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) ||
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(header->binary_type != current_part->binary_type) ||
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(header->image_length >= stm32image_dev.device_size)) {
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WARN("%s: partition %s wrong header\n",
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__func__, current_part->name);
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/* Header not correct, check next offset for backup */
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*stm32_img += current_part->bkp_offset;
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if (*stm32_img > stm32image_dev.device_size) {
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/* No backup found, end of device reached */
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WARN("Out of memory\n");
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result = -ENOMEM;
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break;
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}
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header->magic = 0;
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}
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}
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io_close(backend_handle);
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if (result != 0) {
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return result;
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}
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*length = header->image_length;
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INFO("STM32 Image size : %i\n", *length);
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return 0;
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}
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static int check_header(boot_api_image_header_t *header, uintptr_t buffer)
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{
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uint32_t i;
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uint32_t img_checksum = 0;
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/*
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* Check header/payload validity:
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* - Header magic
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* - Header version
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* - Payload checksum
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*/
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if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) {
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ERROR("Header magic\n");
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return -EINVAL;
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}
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if (header->header_version != BOOT_API_HEADER_VERSION) {
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ERROR("Header version\n");
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return -EINVAL;
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}
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for (i = 0; i < header->image_length; i++) {
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img_checksum += *(uint8_t *)(buffer + i);
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}
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if (header->payload_checksum != img_checksum) {
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ERROR("Checksum: 0x%x (awaited: 0x%x)\n", img_checksum,
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header->payload_checksum);
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return -EINVAL;
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}
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return 0;
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}
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/* Read data from a partition */
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static int stm32image_partition_read(io_entity_t *entity, uintptr_t buffer,
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size_t length, size_t *length_read)
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{
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int result = 0, offset, local_length = 0;
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uint8_t *local_buffer = (uint8_t *)buffer;
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boot_api_image_header_t *header =
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(boot_api_image_header_t *)first_lba_buffer;
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uintptr_t backend_handle;
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assert(entity != NULL);
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assert(buffer != 0U);
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assert(length_read != NULL);
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*length_read = 0U;
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while (*length_read == 0U) {
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if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) {
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/* Check for backup as image is corrupted */
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*stm32_img += current_part->bkp_offset;
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if (*stm32_img >= stm32image_dev.device_size) {
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/* End of device reached */
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result = -ENOMEM;
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break;
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}
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local_buffer = (uint8_t *)buffer;
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result = stm32image_partition_size(entity, &length);
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if (result != 0) {
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break;
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}
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}
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/* Part of image already loaded with the header */
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memcpy(local_buffer, (uint8_t *)first_lba_buffer +
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sizeof(boot_api_image_header_t),
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MAX_LBA_SIZE - sizeof(boot_api_image_header_t));
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local_buffer += MAX_LBA_SIZE - sizeof(boot_api_image_header_t);
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offset = MAX_LBA_SIZE;
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/* New image length to be read */
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local_length = round_up(length -
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((MAX_LBA_SIZE) -
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sizeof(boot_api_image_header_t)),
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stm32image_dev.lba_size);
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if ((header->load_address != 0U) &&
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(header->load_address != buffer)) {
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ERROR("Wrong load address\n");
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panic();
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}
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result = io_open(backend_dev_handle, backend_image_spec,
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&backend_handle);
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if (result != 0) {
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ERROR("%s: io_open (%i)\n", __func__, result);
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break;
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}
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result = io_seek(backend_handle, IO_SEEK_SET,
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*stm32_img + offset);
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if (result != 0) {
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ERROR("%s: io_seek (%i)\n", __func__, result);
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*length_read = 0;
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io_close(backend_handle);
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break;
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}
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result = io_read(backend_handle, (uintptr_t)local_buffer,
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local_length, length_read);
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/* Adding part of size already read from header */
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*length_read += MAX_LBA_SIZE - sizeof(boot_api_image_header_t);
|
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|
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if (result != 0) {
|
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ERROR("%s: io_read (%i)\n", __func__, result);
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*length_read = 0;
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io_close(backend_handle);
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break;
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}
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result = check_header(header, buffer);
|
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if (result != 0) {
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ERROR("Header check failed\n");
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*length_read = 0;
|
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header->magic = 0;
|
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io_close(backend_handle);
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break;
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}
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io_close(backend_handle);
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}
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return result;
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}
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|
||||
/* Close a partition */
|
||||
static int stm32image_partition_close(io_entity_t *entity)
|
||||
{
|
||||
current_part = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Register the stm32image driver with the IO abstraction */
|
||||
int register_io_dev_stm32image(const io_dev_connector_t **dev_con)
|
||||
{
|
||||
int result;
|
||||
|
||||
assert(dev_con != NULL);
|
||||
|
||||
result = io_register_device(&stm32image_dev_info);
|
||||
if (result == 0) {
|
||||
*dev_con = &stm32image_dev_connector;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
@ -0,0 +1,735 @@
|
|||
/*
|
||||
* Copyright (c) 2018, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
#include <delay_timer.h>
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
#include <dt-bindings/reset/stm32mp1-resets.h>
|
||||
#include <errno.h>
|
||||
#include <libfdt.h>
|
||||
#include <mmc.h>
|
||||
#include <mmio.h>
|
||||
#include <platform.h>
|
||||
#include <stm32_sdmmc2.h>
|
||||
#include <stm32mp1_clk.h>
|
||||
#include <stm32mp1_dt.h>
|
||||
#include <stm32mp1_rcc.h>
|
||||
#include <stm32mp1_reset.h>
|
||||
#include <string.h>
|
||||
#include <utils.h>
|
||||
|
||||
/* Registers offsets */
|
||||
#define SDMMC_POWER 0x00U
|
||||
#define SDMMC_CLKCR 0x04U
|
||||
#define SDMMC_ARGR 0x08U
|
||||
#define SDMMC_CMDR 0x0CU
|
||||
#define SDMMC_RESPCMDR 0x10U
|
||||
#define SDMMC_RESP1R 0x14U
|
||||
#define SDMMC_RESP2R 0x18U
|
||||
#define SDMMC_RESP3R 0x1CU
|
||||
#define SDMMC_RESP4R 0x20U
|
||||
#define SDMMC_DTIMER 0x24U
|
||||
#define SDMMC_DLENR 0x28U
|
||||
#define SDMMC_DCTRLR 0x2CU
|
||||
#define SDMMC_DCNTR 0x30U
|
||||
#define SDMMC_STAR 0x34U
|
||||
#define SDMMC_ICR 0x38U
|
||||
#define SDMMC_MASKR 0x3CU
|
||||
#define SDMMC_ACKTIMER 0x40U
|
||||
#define SDMMC_IDMACTRLR 0x50U
|
||||
#define SDMMC_IDMABSIZER 0x54U
|
||||
#define SDMMC_IDMABASE0R 0x58U
|
||||
#define SDMMC_IDMABASE1R 0x5CU
|
||||
#define SDMMC_FIFOR 0x80U
|
||||
|
||||
/* SDMMC power control register */
|
||||
#define SDMMC_POWER_PWRCTRL GENMASK(1, 0)
|
||||
#define SDMMC_POWER_DIRPOL BIT(4)
|
||||
|
||||
/* SDMMC clock control register */
|
||||
#define SDMMC_CLKCR_WIDBUS_4 BIT(14)
|
||||
#define SDMMC_CLKCR_WIDBUS_8 BIT(15)
|
||||
#define SDMMC_CLKCR_NEGEDGE BIT(16)
|
||||
#define SDMMC_CLKCR_HWFC_EN BIT(17)
|
||||
#define SDMMC_CLKCR_SELCLKRX_0 BIT(20)
|
||||
|
||||
/* SDMMC command register */
|
||||
#define SDMMC_CMDR_CMDTRANS BIT(6)
|
||||
#define SDMMC_CMDR_CMDSTOP BIT(7)
|
||||
#define SDMMC_CMDR_WAITRESP GENMASK(9, 8)
|
||||
#define SDMMC_CMDR_WAITRESP_SHORT BIT(8)
|
||||
#define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9)
|
||||
#define SDMMC_CMDR_CPSMEN BIT(12)
|
||||
|
||||
/* SDMMC data control register */
|
||||
#define SDMMC_DCTRLR_DTEN BIT(0)
|
||||
#define SDMMC_DCTRLR_DTDIR BIT(1)
|
||||
#define SDMMC_DCTRLR_DTMODE GENMASK(3, 2)
|
||||
#define SDMMC_DCTRLR_DBLOCKSIZE_0 BIT(4)
|
||||
#define SDMMC_DCTRLR_DBLOCKSIZE_1 BIT(5)
|
||||
#define SDMMC_DCTRLR_DBLOCKSIZE_3 BIT(7)
|
||||
#define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4)
|
||||
#define SDMMC_DCTRLR_FIFORST BIT(13)
|
||||
|
||||
#define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \
|
||||
SDMMC_DCTRLR_DTDIR | \
|
||||
SDMMC_DCTRLR_DTMODE | \
|
||||
SDMMC_DCTRLR_DBLOCKSIZE)
|
||||
#define SDMMC_DBLOCKSIZE_8 (SDMMC_DCTRLR_DBLOCKSIZE_0 | \
|
||||
SDMMC_DCTRLR_DBLOCKSIZE_1)
|
||||
#define SDMMC_DBLOCKSIZE_512 (SDMMC_DCTRLR_DBLOCKSIZE_0 | \
|
||||
SDMMC_DCTRLR_DBLOCKSIZE_3)
|
||||
|
||||
/* SDMMC status register */
|
||||
#define SDMMC_STAR_CCRCFAIL BIT(0)
|
||||
#define SDMMC_STAR_DCRCFAIL BIT(1)
|
||||
#define SDMMC_STAR_CTIMEOUT BIT(2)
|
||||
#define SDMMC_STAR_DTIMEOUT BIT(3)
|
||||
#define SDMMC_STAR_TXUNDERR BIT(4)
|
||||
#define SDMMC_STAR_RXOVERR BIT(5)
|
||||
#define SDMMC_STAR_CMDREND BIT(6)
|
||||
#define SDMMC_STAR_CMDSENT BIT(7)
|
||||
#define SDMMC_STAR_DATAEND BIT(8)
|
||||
#define SDMMC_STAR_DBCKEND BIT(10)
|
||||
#define SDMMC_STAR_DPSMACT BIT(11)
|
||||
#define SDMMC_STAR_RXFIFOHF BIT(15)
|
||||
#define SDMMC_STAR_RXFIFOE BIT(19)
|
||||
#define SDMMC_STAR_IDMATE BIT(27)
|
||||
#define SDMMC_STAR_IDMABTC BIT(28)
|
||||
|
||||
/* SDMMC DMA control register */
|
||||
#define SDMMC_IDMACTRLR_IDMAEN BIT(0)
|
||||
|
||||
#define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \
|
||||
SDMMC_STAR_DCRCFAIL | \
|
||||
SDMMC_STAR_CTIMEOUT | \
|
||||
SDMMC_STAR_DTIMEOUT | \
|
||||
SDMMC_STAR_TXUNDERR | \
|
||||
SDMMC_STAR_RXOVERR | \
|
||||
SDMMC_STAR_CMDREND | \
|
||||
SDMMC_STAR_CMDSENT | \
|
||||
SDMMC_STAR_DATAEND | \
|
||||
SDMMC_STAR_DBCKEND | \
|
||||
SDMMC_STAR_IDMATE | \
|
||||
SDMMC_STAR_IDMABTC)
|
||||
|
||||
#define TIMEOUT_10_MS (plat_get_syscnt_freq2() / 100U)
|
||||
#define TIMEOUT_1_S plat_get_syscnt_freq2()
|
||||
|
||||
#define DT_SDMMC2_COMPAT "st,stm32-sdmmc2"
|
||||
|
||||
static void stm32_sdmmc2_init(void);
|
||||
static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd);
|
||||
static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd);
|
||||
static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width);
|
||||
static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size);
|
||||
static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size);
|
||||
static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size);
|
||||
|
||||
static const struct mmc_ops stm32_sdmmc2_ops = {
|
||||
.init = stm32_sdmmc2_init,
|
||||
.send_cmd = stm32_sdmmc2_send_cmd,
|
||||
.set_ios = stm32_sdmmc2_set_ios,
|
||||
.prepare = stm32_sdmmc2_prepare,
|
||||
.read = stm32_sdmmc2_read,
|
||||
.write = stm32_sdmmc2_write,
|
||||
};
|
||||
|
||||
static struct stm32_sdmmc2_params sdmmc2_params;
|
||||
|
||||
#pragma weak plat_sdmmc2_use_dma
|
||||
bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static void stm32_sdmmc2_init(void)
|
||||
{
|
||||
uint32_t clock_div;
|
||||
uintptr_t base = sdmmc2_params.reg_base;
|
||||
|
||||
clock_div = div_round_up(sdmmc2_params.clk_rate,
|
||||
STM32MP1_MMC_INIT_FREQ * 2);
|
||||
|
||||
mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div |
|
||||
sdmmc2_params.negedge |
|
||||
sdmmc2_params.pin_ckin);
|
||||
|
||||
mmio_write_32(base + SDMMC_POWER,
|
||||
SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol);
|
||||
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
static int stm32_sdmmc2_stop_transfer(void)
|
||||
{
|
||||
struct mmc_cmd cmd_stop;
|
||||
|
||||
zeromem(&cmd_stop, sizeof(struct mmc_cmd));
|
||||
|
||||
cmd_stop.cmd_idx = MMC_CMD(12);
|
||||
cmd_stop.resp_type = MMC_RESPONSE_R1B;
|
||||
|
||||
return stm32_sdmmc2_send_cmd(&cmd_stop);
|
||||
}
|
||||
|
||||
static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd)
|
||||
{
|
||||
uint32_t flags_cmd, status;
|
||||
uint32_t flags_data = 0;
|
||||
int err = 0;
|
||||
uintptr_t base = sdmmc2_params.reg_base;
|
||||
unsigned int cmd_reg, arg_reg, start;
|
||||
|
||||
if (cmd == NULL) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
flags_cmd = SDMMC_STAR_CTIMEOUT;
|
||||
arg_reg = cmd->cmd_arg;
|
||||
|
||||
if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) {
|
||||
mmio_write_32(base + SDMMC_CMDR, 0);
|
||||
}
|
||||
|
||||
cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN;
|
||||
|
||||
if (cmd->resp_type == 0U) {
|
||||
flags_cmd |= SDMMC_STAR_CMDSENT;
|
||||
}
|
||||
|
||||
if ((cmd->resp_type & MMC_RSP_48) != 0U) {
|
||||
if ((cmd->resp_type & MMC_RSP_136) != 0U) {
|
||||
flags_cmd |= SDMMC_STAR_CMDREND;
|
||||
cmd_reg |= SDMMC_CMDR_WAITRESP;
|
||||
} else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) {
|
||||
flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL;
|
||||
cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT;
|
||||
} else {
|
||||
flags_cmd |= SDMMC_STAR_CMDREND;
|
||||
cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC;
|
||||
}
|
||||
}
|
||||
|
||||
switch (cmd->cmd_idx) {
|
||||
case MMC_CMD(1):
|
||||
arg_reg |= OCR_POWERUP;
|
||||
break;
|
||||
case MMC_CMD(8):
|
||||
if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) {
|
||||
cmd_reg |= SDMMC_CMDR_CMDTRANS;
|
||||
}
|
||||
break;
|
||||
case MMC_CMD(12):
|
||||
cmd_reg |= SDMMC_CMDR_CMDSTOP;
|
||||
break;
|
||||
case MMC_CMD(17):
|
||||
case MMC_CMD(18):
|
||||
cmd_reg |= SDMMC_CMDR_CMDTRANS;
|
||||
if (sdmmc2_params.use_dma) {
|
||||
flags_data |= SDMMC_STAR_DCRCFAIL |
|
||||
SDMMC_STAR_DTIMEOUT |
|
||||
SDMMC_STAR_DATAEND |
|
||||
SDMMC_STAR_RXOVERR |
|
||||
SDMMC_STAR_IDMATE;
|
||||
}
|
||||
break;
|
||||
case MMC_ACMD(41):
|
||||
arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4;
|
||||
break;
|
||||
case MMC_ACMD(51):
|
||||
cmd_reg |= SDMMC_CMDR_CMDTRANS;
|
||||
if (sdmmc2_params.use_dma) {
|
||||
flags_data |= SDMMC_STAR_DCRCFAIL |
|
||||
SDMMC_STAR_DTIMEOUT |
|
||||
SDMMC_STAR_DATAEND |
|
||||
SDMMC_STAR_RXOVERR |
|
||||
SDMMC_STAR_IDMATE |
|
||||
SDMMC_STAR_DBCKEND;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) {
|
||||
mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX);
|
||||
}
|
||||
|
||||
mmio_write_32(base + SDMMC_ARGR, arg_reg);
|
||||
|
||||
mmio_write_32(base + SDMMC_CMDR, cmd_reg);
|
||||
|
||||
start = get_timer(0);
|
||||
|
||||
do {
|
||||
status = mmio_read_32(base + SDMMC_STAR);
|
||||
|
||||
if (get_timer(start) > TIMEOUT_10_MS) {
|
||||
err = -ETIMEDOUT;
|
||||
ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n",
|
||||
__func__, cmd->cmd_idx, status);
|
||||
break;
|
||||
}
|
||||
} while ((status & flags_cmd) == 0U);
|
||||
|
||||
if (((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) &&
|
||||
(err == 0)) {
|
||||
if ((status & SDMMC_STAR_CTIMEOUT) != 0U) {
|
||||
err = -ETIMEDOUT;
|
||||
/*
|
||||
* Those timeouts can occur, and framework will handle
|
||||
* the retries. CMD8 is expected to return this timeout
|
||||
* for eMMC
|
||||
*/
|
||||
if (!((cmd->cmd_idx == MMC_CMD(1)) ||
|
||||
(cmd->cmd_idx == MMC_CMD(13)) ||
|
||||
((cmd->cmd_idx == MMC_CMD(8)) &&
|
||||
(cmd->resp_type == MMC_RESPONSE_R7)))) {
|
||||
ERROR("%s: CTIMEOUT (cmd = %d,status = %x)\n",
|
||||
__func__, cmd->cmd_idx, status);
|
||||
}
|
||||
} else {
|
||||
err = -EIO;
|
||||
ERROR("%s: CRCFAIL (cmd = %d,status = %x)\n",
|
||||
__func__, cmd->cmd_idx, status);
|
||||
}
|
||||
}
|
||||
|
||||
if (((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) && (err == 0)) {
|
||||
if ((cmd->cmd_idx == MMC_CMD(9)) &&
|
||||
((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) {
|
||||
/* Need to invert response to match CSD structure */
|
||||
cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R);
|
||||
cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R);
|
||||
cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R);
|
||||
cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R);
|
||||
} else {
|
||||
cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R);
|
||||
if ((cmd_reg & SDMMC_CMDR_WAITRESP) ==
|
||||
SDMMC_CMDR_WAITRESP) {
|
||||
cmd->resp_data[1] = mmio_read_32(base +
|
||||
SDMMC_RESP2R);
|
||||
cmd->resp_data[2] = mmio_read_32(base +
|
||||
SDMMC_RESP3R);
|
||||
cmd->resp_data[3] = mmio_read_32(base +
|
||||
SDMMC_RESP4R);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if ((flags_data == 0U) || (err != 0)) {
|
||||
if (flags_data != 0U) {
|
||||
mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS);
|
||||
}
|
||||
|
||||
mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
|
||||
|
||||
if ((err != 0) && (flags_data != 0U)) {
|
||||
return stm32_sdmmc2_stop_transfer();
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
start = get_timer(0);
|
||||
|
||||
do {
|
||||
status = mmio_read_32(base + SDMMC_STAR);
|
||||
|
||||
if (get_timer(start) > TIMEOUT_10_MS) {
|
||||
ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n",
|
||||
__func__, cmd->cmd_idx, status);
|
||||
err = -ETIMEDOUT;
|
||||
break;
|
||||
}
|
||||
} while ((status & flags_data) == 0U);
|
||||
|
||||
if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL |
|
||||
SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR |
|
||||
SDMMC_STAR_IDMATE)) != 0U) {
|
||||
ERROR("%s: Error flag (cmd = %d,status = %x)\n", __func__,
|
||||
cmd->cmd_idx, status);
|
||||
err = -EIO;
|
||||
}
|
||||
|
||||
mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
|
||||
mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS);
|
||||
|
||||
if (err != 0) {
|
||||
return stm32_sdmmc2_stop_transfer();
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd)
|
||||
{
|
||||
int8_t retry;
|
||||
int err = 0;
|
||||
|
||||
assert(cmd != NULL);
|
||||
|
||||
for (retry = 0; retry <= 3; retry++) {
|
||||
err = stm32_sdmmc2_send_cmd_req(cmd);
|
||||
if (err == 0) {
|
||||
return err;
|
||||
}
|
||||
|
||||
if ((cmd->cmd_idx == MMC_CMD(1)) ||
|
||||
(cmd->cmd_idx == MMC_CMD(13))) {
|
||||
return 0; /* Retry managed by framework */
|
||||
}
|
||||
|
||||
/* Command 8 is expected to fail for eMMC */
|
||||
if (!(cmd->cmd_idx == MMC_CMD(8))) {
|
||||
WARN(" CMD%d, Retry: %d, Error: %d\n",
|
||||
cmd->cmd_idx, retry, err);
|
||||
}
|
||||
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width)
|
||||
{
|
||||
uintptr_t base = sdmmc2_params.reg_base;
|
||||
uint32_t bus_cfg = 0;
|
||||
uint32_t clock_div, max_freq;
|
||||
uint32_t clk_rate = sdmmc2_params.clk_rate;
|
||||
uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq;
|
||||
|
||||
switch (width) {
|
||||
case MMC_BUS_WIDTH_1:
|
||||
break;
|
||||
case MMC_BUS_WIDTH_4:
|
||||
bus_cfg |= SDMMC_CLKCR_WIDBUS_4;
|
||||
break;
|
||||
case MMC_BUS_WIDTH_8:
|
||||
bus_cfg |= SDMMC_CLKCR_WIDBUS_8;
|
||||
break;
|
||||
default:
|
||||
panic();
|
||||
break;
|
||||
}
|
||||
|
||||
if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) {
|
||||
if (max_bus_freq >= 52000000U) {
|
||||
max_freq = STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ;
|
||||
} else {
|
||||
max_freq = STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ;
|
||||
}
|
||||
} else {
|
||||
if (max_bus_freq >= 50000000U) {
|
||||
max_freq = STM32MP1_SD_HIGH_SPEED_MAX_FREQ;
|
||||
} else {
|
||||
max_freq = STM32MP1_SD_NORMAL_SPEED_MAX_FREQ;
|
||||
}
|
||||
}
|
||||
|
||||
clock_div = div_round_up(clk_rate, max_freq * 2);
|
||||
|
||||
mmio_write_32(base + SDMMC_CLKCR,
|
||||
SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg |
|
||||
sdmmc2_params.negedge |
|
||||
sdmmc2_params.pin_ckin);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size)
|
||||
{
|
||||
struct mmc_cmd cmd;
|
||||
int ret;
|
||||
uintptr_t base = sdmmc2_params.reg_base;
|
||||
uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR;
|
||||
|
||||
if (size == 8U) {
|
||||
data_ctrl |= SDMMC_DBLOCKSIZE_8;
|
||||
} else {
|
||||
data_ctrl |= SDMMC_DBLOCKSIZE_512;
|
||||
}
|
||||
|
||||
sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf);
|
||||
|
||||
if (sdmmc2_params.use_dma) {
|
||||
inv_dcache_range(buf, size);
|
||||
}
|
||||
|
||||
/* Prepare CMD 16*/
|
||||
mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX);
|
||||
|
||||
mmio_write_32(base + SDMMC_DLENR, 0);
|
||||
|
||||
mmio_clrsetbits_32(base + SDMMC_DCTRLR,
|
||||
SDMMC_DCTRLR_CLEAR_MASK, SDMMC_DCTRLR_DTDIR);
|
||||
|
||||
zeromem(&cmd, sizeof(struct mmc_cmd));
|
||||
|
||||
cmd.cmd_idx = MMC_CMD(16);
|
||||
if (size > MMC_BLOCK_SIZE) {
|
||||
cmd.cmd_arg = MMC_BLOCK_SIZE;
|
||||
} else {
|
||||
cmd.cmd_arg = size;
|
||||
}
|
||||
|
||||
cmd.resp_type = MMC_RESPONSE_R1;
|
||||
|
||||
ret = stm32_sdmmc2_send_cmd(&cmd);
|
||||
if (ret != 0) {
|
||||
ERROR("CMD16 failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Prepare data command */
|
||||
mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX);
|
||||
|
||||
mmio_write_32(base + SDMMC_DLENR, size);
|
||||
|
||||
if (sdmmc2_params.use_dma) {
|
||||
mmio_write_32(base + SDMMC_IDMACTRLR,
|
||||
SDMMC_IDMACTRLR_IDMAEN);
|
||||
mmio_write_32(base + SDMMC_IDMABASE0R, buf);
|
||||
|
||||
flush_dcache_range(buf, size);
|
||||
}
|
||||
|
||||
mmio_clrsetbits_32(base + SDMMC_DCTRLR,
|
||||
SDMMC_DCTRLR_CLEAR_MASK,
|
||||
data_ctrl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size)
|
||||
{
|
||||
uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL |
|
||||
SDMMC_STAR_DTIMEOUT;
|
||||
uint32_t flags = error_flags | SDMMC_STAR_DATAEND;
|
||||
uint32_t status;
|
||||
uint32_t *buffer;
|
||||
uintptr_t base = sdmmc2_params.reg_base;
|
||||
uintptr_t fifo_reg = base + SDMMC_FIFOR;
|
||||
unsigned int start;
|
||||
int ret;
|
||||
|
||||
/* Assert buf is 4 bytes aligned */
|
||||
assert((buf & GENMASK(1, 0)) == 0U);
|
||||
|
||||
buffer = (uint32_t *)buf;
|
||||
|
||||
if (sdmmc2_params.use_dma) {
|
||||
inv_dcache_range(buf, size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (size <= MMC_BLOCK_SIZE) {
|
||||
flags |= SDMMC_STAR_DBCKEND;
|
||||
}
|
||||
|
||||
start = get_timer(0);
|
||||
|
||||
do {
|
||||
status = mmio_read_32(base + SDMMC_STAR);
|
||||
|
||||
if ((status & error_flags) != 0U) {
|
||||
ERROR("%s: Read error (status = %x)\n", __func__,
|
||||
status);
|
||||
mmio_write_32(base + SDMMC_DCTRLR,
|
||||
SDMMC_DCTRLR_FIFORST);
|
||||
|
||||
mmio_write_32(base + SDMMC_ICR,
|
||||
SDMMC_STATIC_FLAGS);
|
||||
|
||||
ret = stm32_sdmmc2_stop_transfer();
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
if (get_timer(start) > TIMEOUT_1_S) {
|
||||
ERROR("%s: timeout 1s (status = %x)\n",
|
||||
__func__, status);
|
||||
mmio_write_32(base + SDMMC_ICR,
|
||||
SDMMC_STATIC_FLAGS);
|
||||
|
||||
ret = stm32_sdmmc2_stop_transfer();
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
if (size < (8U * sizeof(uint32_t))) {
|
||||
if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) &&
|
||||
((status & SDMMC_STAR_RXFIFOE) == 0U)) {
|
||||
*buffer = mmio_read_32(fifo_reg);
|
||||
buffer++;
|
||||
}
|
||||
} else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) {
|
||||
uint32_t count;
|
||||
|
||||
/* Read data from SDMMC Rx FIFO */
|
||||
for (count = 0; count < 8U; count++) {
|
||||
*buffer = mmio_read_32(fifo_reg);
|
||||
buffer++;
|
||||
}
|
||||
}
|
||||
} while ((status & flags) == 0U);
|
||||
|
||||
mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
|
||||
|
||||
if ((status & SDMMC_STAR_DPSMACT) != 0U) {
|
||||
WARN("%s: DPSMACT=1, send stop\n", __func__);
|
||||
return stm32_sdmmc2_stop_transfer();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_sdmmc2_dt_get_config(void)
|
||||
{
|
||||
int sdmmc_node;
|
||||
void *fdt = NULL;
|
||||
const fdt32_t *cuint;
|
||||
|
||||
if (fdt_get_address(&fdt) == 0) {
|
||||
return -FDT_ERR_NOTFOUND;
|
||||
}
|
||||
|
||||
if (fdt == NULL) {
|
||||
return -FDT_ERR_NOTFOUND;
|
||||
}
|
||||
|
||||
sdmmc_node = fdt_node_offset_by_compatible(fdt, -1, DT_SDMMC2_COMPAT);
|
||||
|
||||
while (sdmmc_node != -FDT_ERR_NOTFOUND) {
|
||||
cuint = fdt_getprop(fdt, sdmmc_node, "reg", NULL);
|
||||
if (cuint == NULL) {
|
||||
continue;
|
||||
}
|
||||
|
||||
if (fdt32_to_cpu(*cuint) == sdmmc2_params.reg_base) {
|
||||
break;
|
||||
}
|
||||
|
||||
sdmmc_node = fdt_node_offset_by_compatible(fdt, sdmmc_node,
|
||||
DT_SDMMC2_COMPAT);
|
||||
}
|
||||
|
||||
if (sdmmc_node == -FDT_ERR_NOTFOUND) {
|
||||
return -FDT_ERR_NOTFOUND;
|
||||
}
|
||||
|
||||
if (fdt_check_status(sdmmc_node) == 0) {
|
||||
return -FDT_ERR_NOTFOUND;
|
||||
}
|
||||
|
||||
if (dt_set_pinctrl_config(sdmmc_node) != 0) {
|
||||
return -FDT_ERR_BADVALUE;
|
||||
}
|
||||
|
||||
cuint = fdt_getprop(fdt, sdmmc_node, "clocks", NULL);
|
||||
if (cuint == NULL) {
|
||||
return -FDT_ERR_NOTFOUND;
|
||||
}
|
||||
|
||||
cuint++;
|
||||
sdmmc2_params.clock_id = fdt32_to_cpu(*cuint);
|
||||
|
||||
cuint = fdt_getprop(fdt, sdmmc_node, "resets", NULL);
|
||||
if (cuint == NULL) {
|
||||
return -FDT_ERR_NOTFOUND;
|
||||
}
|
||||
|
||||
cuint++;
|
||||
sdmmc2_params.reset_id = fdt32_to_cpu(*cuint);
|
||||
|
||||
if ((fdt_getprop(fdt, sdmmc_node, "st,pin-ckin", NULL)) != NULL) {
|
||||
sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0;
|
||||
}
|
||||
|
||||
if ((fdt_getprop(fdt, sdmmc_node, "st,dirpol", NULL)) != NULL) {
|
||||
sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL;
|
||||
}
|
||||
|
||||
if ((fdt_getprop(fdt, sdmmc_node, "st,negedge", NULL)) != NULL) {
|
||||
sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE;
|
||||
}
|
||||
|
||||
cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL);
|
||||
if (cuint != NULL) {
|
||||
switch (fdt32_to_cpu(*cuint)) {
|
||||
case 4:
|
||||
sdmmc2_params.bus_width = MMC_BUS_WIDTH_4;
|
||||
break;
|
||||
|
||||
case 8:
|
||||
sdmmc2_params.bus_width = MMC_BUS_WIDTH_8;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long long stm32_sdmmc2_mmc_get_device_size(void)
|
||||
{
|
||||
return sdmmc2_params.device_info->device_size;
|
||||
}
|
||||
|
||||
int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params)
|
||||
{
|
||||
int ret;
|
||||
|
||||
assert((params != NULL) &&
|
||||
((params->reg_base & MMC_BLOCK_MASK) == 0U) &&
|
||||
((params->bus_width == MMC_BUS_WIDTH_1) ||
|
||||
(params->bus_width == MMC_BUS_WIDTH_4) ||
|
||||
(params->bus_width == MMC_BUS_WIDTH_8)));
|
||||
|
||||
memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params));
|
||||
|
||||
if (stm32_sdmmc2_dt_get_config() != 0) {
|
||||
ERROR("%s: DT error\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ret = stm32mp1_clk_enable(sdmmc2_params.clock_id);
|
||||
if (ret != 0) {
|
||||
ERROR("%s: clock %d failed\n", __func__,
|
||||
sdmmc2_params.clock_id);
|
||||
return ret;
|
||||
}
|
||||
|
||||
stm32mp1_reset_assert(sdmmc2_params.reset_id);
|
||||
udelay(2);
|
||||
stm32mp1_reset_deassert(sdmmc2_params.reset_id);
|
||||
mdelay(1);
|
||||
|
||||
sdmmc2_params.clk_rate = stm32mp1_clk_get_rate(sdmmc2_params.clock_id);
|
||||
|
||||
return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate,
|
||||
sdmmc2_params.bus_width, sdmmc2_params.flags,
|
||||
sdmmc2_params.device_info);
|
||||
}
|
||||
|
|
@ -77,7 +77,13 @@
|
|||
/* NT_FW_CONFIG */
|
||||
#define NT_FW_CONFIG_ID U(27)
|
||||
|
||||
/* GPT Partition */
|
||||
#define GPT_IMAGE_ID U(28)
|
||||
|
||||
/* Binary with STM32 header */
|
||||
#define STM32_IMAGE_ID U(29)
|
||||
|
||||
/* Define size of the array */
|
||||
#define MAX_NUMBER_IDS U(28)
|
||||
#define MAX_NUMBER_IDS U(30)
|
||||
|
||||
#endif /* __TBBR_IMG_DEF_H__ */
|
||||
|
|
|
|||
|
|
@ -22,6 +22,8 @@ typedef enum {
|
|||
IO_TYPE_DUMMY,
|
||||
IO_TYPE_FIRMWARE_IMAGE_PACKAGE,
|
||||
IO_TYPE_BLOCK,
|
||||
IO_TYPE_MMC,
|
||||
IO_TYPE_STM32IMAGE,
|
||||
IO_TYPE_MAX
|
||||
} io_type_t;
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IO_MMC_H
|
||||
#define IO_MMC_H
|
||||
|
||||
#include <io_driver.h>
|
||||
|
||||
int register_io_dev_mmc(const io_dev_connector_t **dev_con);
|
||||
|
||||
#endif /* IO_MMC_H */
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IO_STM32IMAGE_H
|
||||
#define IO_STM32IMAGE_H
|
||||
|
||||
#include <io_driver.h>
|
||||
#include <partition.h>
|
||||
|
||||
#define MAX_LBA_SIZE 512
|
||||
#define MAX_PART_NAME_SIZE (EFI_NAMELEN + 1)
|
||||
#define STM32_PART_NUM (PLAT_PARTITION_MAX_ENTRIES - STM32_TF_A_COPIES)
|
||||
|
||||
struct stm32image_part_info {
|
||||
char name[MAX_PART_NAME_SIZE];
|
||||
uint32_t binary_type;
|
||||
uintptr_t part_offset;
|
||||
uint32_t bkp_offset;
|
||||
};
|
||||
|
||||
struct stm32image_device_info {
|
||||
struct stm32image_part_info part_info[STM32_PART_NUM];
|
||||
uint32_t device_size;
|
||||
uint32_t lba_size;
|
||||
};
|
||||
|
||||
int register_io_dev_stm32image(const io_dev_connector_t **dev_con);
|
||||
|
||||
#endif /* IO_STM32IMAGE_H */
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef STM32_SDMMC2_H
|
||||
#define STM32_SDMMC2_H
|
||||
|
||||
#include <mmc.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
struct stm32_sdmmc2_params {
|
||||
uintptr_t reg_base;
|
||||
unsigned int clk_rate;
|
||||
unsigned int bus_width;
|
||||
unsigned int flags;
|
||||
struct mmc_device_info *device_info;
|
||||
unsigned int pin_ckin;
|
||||
unsigned int negedge;
|
||||
unsigned int dirpol;
|
||||
unsigned int clock_id;
|
||||
unsigned int reset_id;
|
||||
bool use_dma;
|
||||
};
|
||||
|
||||
unsigned long long stm32_sdmmc2_mmc_get_device_size(void);
|
||||
int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params);
|
||||
bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory);
|
||||
|
||||
#endif /* STM32_SDMMC2_H */
|
||||
|
|
@ -8,12 +8,18 @@
|
|||
#include <assert.h>
|
||||
#include <boot_api.h>
|
||||
#include <debug.h>
|
||||
#include <io_block.h>
|
||||
#include <io_driver.h>
|
||||
#include <io_dummy.h>
|
||||
#include <io_mmc.h>
|
||||
#include <io_stm32image.h>
|
||||
#include <io_storage.h>
|
||||
#include <mmc.h>
|
||||
#include <mmio.h>
|
||||
#include <partition.h>
|
||||
#include <platform.h>
|
||||
#include <platform_def.h>
|
||||
#include <stm32_sdmmc2.h>
|
||||
#include <stm32mp1_private.h>
|
||||
#include <stm32mp1_rcc.h>
|
||||
#include <string.h>
|
||||
|
|
@ -24,6 +30,50 @@ static const io_dev_connector_t *dummy_dev_con;
|
|||
static uintptr_t dummy_dev_handle;
|
||||
static uintptr_t dummy_dev_spec;
|
||||
|
||||
static uintptr_t image_dev_handle;
|
||||
|
||||
static io_block_spec_t gpt_block_spec = {
|
||||
.offset = 0,
|
||||
.length = 34 * MMC_BLOCK_SIZE, /* Size of GPT table */
|
||||
};
|
||||
|
||||
uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE);
|
||||
|
||||
static const io_block_dev_spec_t mmc_block_dev_spec = {
|
||||
/* It's used as temp buffer in block driver */
|
||||
.buffer = {
|
||||
.offset = (size_t)&block_buffer,
|
||||
.length = MMC_BLOCK_SIZE,
|
||||
},
|
||||
.ops = {
|
||||
.read = mmc_read_blocks,
|
||||
.write = NULL,
|
||||
},
|
||||
.block_size = MMC_BLOCK_SIZE,
|
||||
};
|
||||
|
||||
static uintptr_t storage_dev_handle;
|
||||
static const io_dev_connector_t *mmc_dev_con;
|
||||
|
||||
#define IMG_IDX_BL33 0
|
||||
|
||||
static const struct stm32image_part_info bl33_partition_spec = {
|
||||
.name = BL33_IMAGE_NAME,
|
||||
.binary_type = BL33_BINARY_TYPE,
|
||||
};
|
||||
|
||||
static struct stm32image_device_info stm32image_dev_info_spec = {
|
||||
.lba_size = MMC_BLOCK_SIZE,
|
||||
.part_info[IMG_IDX_BL33] = {
|
||||
.name = BL33_IMAGE_NAME,
|
||||
.binary_type = BL33_BINARY_TYPE,
|
||||
},
|
||||
};
|
||||
|
||||
static io_block_spec_t stm32image_block_spec;
|
||||
|
||||
static const io_dev_connector_t *stm32image_dev_con;
|
||||
|
||||
static const io_block_spec_t bl32_block_spec = {
|
||||
.offset = BL32_BASE,
|
||||
.length = STM32MP1_BL32_SIZE
|
||||
|
|
@ -35,6 +85,8 @@ static const io_block_spec_t bl2_block_spec = {
|
|||
};
|
||||
|
||||
static int open_dummy(const uintptr_t spec);
|
||||
static int open_image(const uintptr_t spec);
|
||||
static int open_storage(const uintptr_t spec);
|
||||
|
||||
struct plat_io_policy {
|
||||
uintptr_t *dev_handle;
|
||||
|
|
@ -53,6 +105,21 @@ static const struct plat_io_policy policies[] = {
|
|||
.image_spec = (uintptr_t)&bl32_block_spec,
|
||||
.check = open_dummy
|
||||
},
|
||||
[BL33_IMAGE_ID] = {
|
||||
.dev_handle = &image_dev_handle,
|
||||
.image_spec = (uintptr_t)&bl33_partition_spec,
|
||||
.check = open_image
|
||||
},
|
||||
[GPT_IMAGE_ID] = {
|
||||
.dev_handle = &storage_dev_handle,
|
||||
.image_spec = (uintptr_t)&gpt_block_spec,
|
||||
.check = open_storage
|
||||
},
|
||||
[STM32_IMAGE_ID] = {
|
||||
.dev_handle = &storage_dev_handle,
|
||||
.image_spec = (uintptr_t)&stm32image_block_spec,
|
||||
.check = open_storage
|
||||
}
|
||||
};
|
||||
|
||||
static int open_dummy(const uintptr_t spec)
|
||||
|
|
@ -60,6 +127,16 @@ static int open_dummy(const uintptr_t spec)
|
|||
return io_dev_init(dummy_dev_handle, 0);
|
||||
}
|
||||
|
||||
static int open_image(const uintptr_t spec)
|
||||
{
|
||||
return io_dev_init(image_dev_handle, 0);
|
||||
}
|
||||
|
||||
static int open_storage(const uintptr_t spec)
|
||||
{
|
||||
return io_dev_init(storage_dev_handle, 0);
|
||||
}
|
||||
|
||||
static void print_boot_device(boot_api_context_t *boot_context)
|
||||
{
|
||||
switch (boot_context->boot_interface_selected) {
|
||||
|
|
@ -149,6 +226,9 @@ static void print_reset_reason(void)
|
|||
void stm32mp1_io_setup(void)
|
||||
{
|
||||
int io_result __unused;
|
||||
struct stm32_sdmmc2_params params;
|
||||
struct mmc_device_info device_info;
|
||||
uintptr_t mmc_default_instance;
|
||||
boot_api_context_t *boot_context =
|
||||
(boot_api_context_t *)stm32mp1_get_boot_ctx_address();
|
||||
|
||||
|
|
@ -168,6 +248,93 @@ void stm32mp1_io_setup(void)
|
|||
io_result = io_dev_open(dummy_dev_con, dummy_dev_spec,
|
||||
&dummy_dev_handle);
|
||||
assert(io_result == 0);
|
||||
|
||||
switch (boot_context->boot_interface_selected) {
|
||||
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
|
||||
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
|
||||
dmb();
|
||||
|
||||
memset(¶ms, 0, sizeof(struct stm32_sdmmc2_params));
|
||||
|
||||
if (boot_context->boot_interface_selected ==
|
||||
BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC) {
|
||||
device_info.mmc_dev_type = MMC_IS_EMMC;
|
||||
mmc_default_instance = STM32MP1_SDMMC2_BASE;
|
||||
} else {
|
||||
device_info.mmc_dev_type = MMC_IS_SD;
|
||||
mmc_default_instance = STM32MP1_SDMMC1_BASE;
|
||||
}
|
||||
|
||||
switch (boot_context->boot_interface_instance) {
|
||||
case 1:
|
||||
params.reg_base = STM32MP1_SDMMC1_BASE;
|
||||
break;
|
||||
case 2:
|
||||
params.reg_base = STM32MP1_SDMMC2_BASE;
|
||||
break;
|
||||
case 3:
|
||||
params.reg_base = STM32MP1_SDMMC3_BASE;
|
||||
break;
|
||||
default:
|
||||
WARN("SDMMC instance not found, using default\n");
|
||||
params.reg_base = mmc_default_instance;
|
||||
break;
|
||||
}
|
||||
|
||||
params.device_info = &device_info;
|
||||
stm32_sdmmc2_mmc_init(¶ms);
|
||||
|
||||
/* Open MMC as a block device to read GPT table */
|
||||
io_result = register_io_dev_block(&mmc_dev_con);
|
||||
if (io_result != 0) {
|
||||
panic();
|
||||
}
|
||||
|
||||
io_result = io_dev_open(mmc_dev_con,
|
||||
(uintptr_t)&mmc_block_dev_spec,
|
||||
&storage_dev_handle);
|
||||
assert(io_result == 0);
|
||||
|
||||
partition_init(GPT_IMAGE_ID);
|
||||
|
||||
io_result = io_dev_close(storage_dev_handle);
|
||||
assert(io_result == 0);
|
||||
|
||||
stm32image_dev_info_spec.device_size =
|
||||
stm32_sdmmc2_mmc_get_device_size();
|
||||
stm32image_dev_info_spec.part_info[IMG_IDX_BL33].part_offset =
|
||||
get_partition_entry(BL33_IMAGE_NAME)->start;
|
||||
stm32image_dev_info_spec.part_info[IMG_IDX_BL33].bkp_offset =
|
||||
get_partition_entry(BL33_IMAGE_NAME)->length;
|
||||
|
||||
stm32image_block_spec.offset = 0;
|
||||
stm32image_block_spec.length =
|
||||
get_partition_entry(BL33_IMAGE_NAME)->length;
|
||||
|
||||
/*
|
||||
* Re-open MMC with io_mmc, for better perfs compared to
|
||||
* io_block.
|
||||
*/
|
||||
io_result = register_io_dev_mmc(&mmc_dev_con);
|
||||
assert(io_result == 0);
|
||||
|
||||
io_result = io_dev_open(mmc_dev_con, 0, &storage_dev_handle);
|
||||
assert(io_result == 0);
|
||||
|
||||
io_result = register_io_dev_stm32image(&stm32image_dev_con);
|
||||
assert(io_result == 0);
|
||||
|
||||
io_result = io_dev_open(stm32image_dev_con,
|
||||
(uintptr_t)&stm32image_dev_info_spec,
|
||||
&image_dev_handle);
|
||||
assert(io_result == 0);
|
||||
break;
|
||||
|
||||
default:
|
||||
ERROR("Boot interface %d not supported\n",
|
||||
boot_context->boot_interface_selected);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2017, STMicroelectronics - All Rights Reserved
|
||||
* Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -8,6 +8,7 @@
|
|||
#define __BOOT_API_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
|
||||
/*
|
||||
* Possible value of boot context field 'boot_interface_sel'
|
||||
|
|
@ -229,7 +230,9 @@ typedef struct {
|
|||
*/
|
||||
uint8_t ecc_pubk[BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES];
|
||||
/* Pad up to 256 byte total size */
|
||||
uint8_t pad[84];
|
||||
uint8_t pad[83];
|
||||
/* Add binary type information */
|
||||
uint8_t binary_type;
|
||||
} __packed boot_api_image_header_t;
|
||||
|
||||
#endif /* __BOOT_API_H */
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
|
||||
/* SSBL = second stage boot loader */
|
||||
#define BL33_IMAGE_NAME "ssbl"
|
||||
#define BL33_BINARY_TYPE U(0x0)
|
||||
|
||||
#define STM32MP1_PRIMARY_CPU U(0x0)
|
||||
|
||||
|
|
@ -39,6 +40,7 @@
|
|||
|
||||
#define MAX_IO_DEVICES 4
|
||||
#define MAX_IO_HANDLES 4
|
||||
#define MAX_IO_BLOCK_DEVICES 1
|
||||
|
||||
/*******************************************************************************
|
||||
* BL2 specific defines.
|
||||
|
|
|
|||
|
|
@ -14,8 +14,15 @@ STM32_TF_VERSION ?= 0
|
|||
# Not needed for Cortex-A7
|
||||
WORKAROUND_CVE_2017_5715:= 0
|
||||
|
||||
# Number of TF-A copies in the device
|
||||
STM32_TF_A_COPIES := 2
|
||||
$(eval $(call add_define,STM32_TF_A_COPIES))
|
||||
PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 1)))
|
||||
$(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
|
||||
|
||||
PLAT_INCLUDES := -Iplat/st/stm32mp1/include/
|
||||
PLAT_INCLUDES += -Iinclude/common/tbbr
|
||||
PLAT_INCLUDES += -Iinclude/drivers/partition
|
||||
PLAT_INCLUDES += -Iinclude/drivers/st
|
||||
|
||||
# Device tree
|
||||
|
|
@ -56,11 +63,19 @@ PLAT_BL_COMMON_SOURCES += ${LIBFDT_SRCS} \
|
|||
plat/st/stm32mp1/stm32mp1_helper.S \
|
||||
plat/st/stm32mp1/stm32mp1_security.c
|
||||
|
||||
BL2_SOURCES += drivers/io/io_dummy.c \
|
||||
BL2_SOURCES += drivers/io/io_block.c \
|
||||
drivers/io/io_dummy.c \
|
||||
drivers/io/io_storage.c \
|
||||
drivers/st/io/io_stm32image.c \
|
||||
plat/st/stm32mp1/bl2_io_storage.c \
|
||||
plat/st/stm32mp1/bl2_plat_setup.c
|
||||
|
||||
BL2_SOURCES += drivers/mmc/mmc.c \
|
||||
drivers/partition/gpt.c \
|
||||
drivers/partition/partition.c \
|
||||
drivers/st/io/io_mmc.c \
|
||||
drivers/st/mmc/stm32_sdmmc2.c
|
||||
|
||||
BL2_SOURCES += drivers/st/ddr/stm32mp1_ddr.c \
|
||||
drivers/st/ddr/stm32mp1_ram.c
|
||||
|
||||
|
|
|
|||
|
|
@ -155,10 +155,9 @@ enum ddr_type {
|
|||
#define STM32MP1_SDMMC2_BASE U(0x58007000)
|
||||
#define STM32MP1_SDMMC3_BASE U(0x48004000)
|
||||
|
||||
#define STM32MP1_SD_INIT_FREQ 400000 /*400 KHz*/
|
||||
#define STM32MP1_MMC_INIT_FREQ 400000 /*400 KHz*/
|
||||
#define STM32MP1_SD_NORMAL_SPEED_MAX_FREQ 25000000 /*25 MHz*/
|
||||
#define STM32MP1_SD_HIGH_SPEED_MAX_FREQ 50000000 /*50 MHz*/
|
||||
#define STM32MP1_EMMC_INIT_FREQ STM32MP1_SD_INIT_FREQ
|
||||
#define STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ 26000000 /*26 MHz*/
|
||||
#define STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ 52000000 /*52 MHz*/
|
||||
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
#define VER_MINOR 1
|
||||
#define VER_VARIANT 0
|
||||
#define HEADER_VERSION_V1 0x1
|
||||
#define TF_BINARY_TYPE 0x0
|
||||
#define TF_BINARY_TYPE 0x10
|
||||
|
||||
/* Default option : bit0 => no signature */
|
||||
#define HEADER_DEFAULT_OPTION (__cpu_to_le32(0x00000001))
|
||||
|
|
|
|||
Loading…
Reference in New Issue