Merge pull request #452 from vwadekar/tegra-new-platform-apis-v2
Tegra new platform apis v2
This commit is contained in:
commit
05a91fb008
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@ -36,9 +36,9 @@
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#include <tegra_def.h>
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/* Global functions */
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.globl platform_is_primary_cpu
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.globl platform_get_core_pos
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.globl platform_get_entrypoint
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_get_my_entrypoint
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.globl plat_secondary_cold_boot_setup
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.globl platform_mem_init
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.globl plat_crash_console_init
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@ -47,7 +47,7 @@
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.globl plat_reset_handler
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/* Global variables */
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.globl sec_entry_point
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.globl tegra_sec_entry_point
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.globl ns_image_entrypoint
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.globl tegra_bl31_phys_base
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@ -115,28 +115,47 @@
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.endm
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/* -----------------------------------------------------
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* int platform_is_primary_cpu(int mpidr);
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* unsigned int plat_is_my_cpu_primary(void);
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*
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* This function checks if this is the Primary CPU
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* -----------------------------------------------------
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*/
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func platform_is_primary_cpu
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #TEGRA_PRIMARY_CPU
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cset x0, eq
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ret
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endfunc platform_is_primary_cpu
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* int platform_get_core_pos(int mpidr);
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* unsigned int plat_my_core_pos(void);
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*
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* With this function: CorePos = CoreId
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* result: CorePos = CoreId + (ClusterId << 2)
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* -----------------------------------------------------
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*/
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func platform_get_core_pos
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and x0, x0, #MPIDR_CPU_MASK
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func plat_my_core_pos
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mrs x0, mpidr_el1
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc platform_get_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned long plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between
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* a cold and warm boot. If the tegra_sec_entry_point for
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* this CPU is present, then it's a warm boot.
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*
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* -----------------------------------------------------
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*/
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func plat_get_my_entrypoint
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adr x1, tegra_sec_entry_point
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ldr x0, [x1]
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ret
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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@ -151,22 +170,6 @@ func plat_secondary_cold_boot_setup
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ret
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endfunc plat_secondary_cold_boot_setup
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/* -----------------------------------------------------
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* void platform_get_entrypoint (unsigned int mpidr);
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*
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* Main job of this routine is to distinguish between
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* a cold and warm boot. If the sec_entry_point for
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* this CPU is present, then it's a warm boot.
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*
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* -----------------------------------------------------
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*/
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func platform_get_entrypoint
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and x0, x0, #MPIDR_CPU_MASK
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adr x1, sec_entry_point
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ldr x0, [x1, x0, lsl #3]
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ret
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endfunc platform_get_entrypoint
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/* --------------------------------------------------------
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* void platform_mem_init (void);
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*
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@ -336,8 +339,7 @@ restore_oslock:
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* Get secure world's entry point and jump to it
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* --------------------------------------------------
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*/
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mrs x0, mpidr_el1
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bl platform_get_entrypoint
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bl plat_get_my_entrypoint
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br x0
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endfunc tegra_secure_entrypoint
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@ -345,13 +347,11 @@ endfunc tegra_secure_entrypoint
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.align 3
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/* --------------------------------------------------
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* Per-CPU Secure entry point - resume from suspend
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* CPU Secure entry point - resume from suspend
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* --------------------------------------------------
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*/
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sec_entry_point:
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.rept PLATFORM_CORE_COUNT
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tegra_sec_entry_point:
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.quad 0
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.endr
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/* --------------------------------------------------
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* NS world's cold boot entry point
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@ -98,9 +98,9 @@ static void tegra_fc_prepare_suspend(int cpu_id, uint32_t csr)
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}
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/*******************************************************************************
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* Suspend the current CPU
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* Powerdn the current CPU
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******************************************************************************/
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void tegra_fc_cpu_idle(uint32_t mpidr)
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void tegra_fc_cpu_powerdn(uint32_t mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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@ -51,6 +51,7 @@ BL31_SOURCES += drivers/arm/gic/gic_v2.c \
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drivers/delay_timer/delay_timer.c \
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drivers/ti/uart/16550_console.S \
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plat/common/aarch64/platform_mp_stack.S \
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plat/common/aarch64/plat_psci_common.c \
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${COMMON_DIR}/aarch64/tegra_helpers.S \
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${COMMON_DIR}/drivers/memctrl/memctrl.c \
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${COMMON_DIR}/drivers/pmc/pmc.c \
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@ -44,35 +44,34 @@
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#include <tegra_private.h>
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extern uint64_t tegra_bl31_phys_base;
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extern uint64_t sec_entry_point[PLATFORM_CORE_COUNT];
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static int system_suspended;
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extern uint64_t tegra_sec_entry_point;
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/*
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* The following platform setup functions are weakly defined. They
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* provide typical implementations that will be overridden by a SoC.
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*/
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#pragma weak tegra_soc_prepare_cpu_suspend
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#pragma weak tegra_soc_prepare_cpu_on
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#pragma weak tegra_soc_prepare_cpu_off
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#pragma weak tegra_soc_prepare_cpu_on_finish
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#pragma weak tegra_soc_pwr_domain_suspend
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#pragma weak tegra_soc_pwr_domain_on
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#pragma weak tegra_soc_pwr_domain_off
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#pragma weak tegra_soc_pwr_domain_on_finish
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#pragma weak tegra_soc_prepare_system_reset
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int tegra_soc_prepare_cpu_suspend(unsigned int id, unsigned int afflvl)
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int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int tegra_soc_prepare_cpu_on(unsigned long mpidr)
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int tegra_soc_pwr_domain_on(u_register_t mpidr)
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{
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_prepare_cpu_off(unsigned long mpidr)
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int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
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{
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_prepare_cpu_on_finish(unsigned long mpidr)
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int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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return PSCI_E_SUCCESS;
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}
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@ -83,33 +82,25 @@ int tegra_soc_prepare_system_reset(void)
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}
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/*******************************************************************************
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* Track system suspend entry.
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******************************************************************************/
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void tegra_pm_system_suspend_entry(void)
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* This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND`
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* call to get the `power_state` parameter. This allows the platform to encode
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* the appropriate State-ID field within the `power_state` parameter which can
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* be utilized in `pwr_domain_suspend()` to suspend to system affinity level.
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******************************************************************************/
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void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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system_suspended = 1;
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}
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/* lower affinities use PLAT_MAX_OFF_STATE */
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for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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/*******************************************************************************
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* Track system suspend exit.
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******************************************************************************/
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void tegra_pm_system_suspend_exit(void)
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{
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system_suspended = 0;
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}
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/*******************************************************************************
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* Get the system suspend state.
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******************************************************************************/
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int tegra_system_suspended(void)
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{
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return system_suspended;
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/* max affinity uses system suspend state id */
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req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PSTATE_ID_SOC_POWERDN;
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}
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/*******************************************************************************
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* Handler called when an affinity instance is about to enter standby.
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******************************************************************************/
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void tegra_affinst_standby(unsigned int power_state)
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void tegra_cpu_standby(plat_local_state_t cpu_state)
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{
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/*
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* Enter standby state
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@ -119,132 +110,45 @@ void tegra_affinst_standby(unsigned int power_state)
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wfi();
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}
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/*******************************************************************************
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* This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND`
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* call to get the `power_state` parameter. This allows the platform to encode
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* the appropriate State-ID field within the `power_state` parameter which can
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* be utilized in `affinst_suspend()` to suspend to system affinity level.
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******************************************************************************/
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unsigned int tegra_get_sys_suspend_power_state(void)
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{
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unsigned int power_state;
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power_state = psci_make_powerstate(PLAT_SYS_SUSPEND_STATE_ID,
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PSTATE_TYPE_POWERDOWN, MPIDR_AFFLVL2);
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return power_state;
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}
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/*******************************************************************************
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* Handler called to check the validity of the power state parameter.
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******************************************************************************/
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int32_t tegra_validate_power_state(unsigned int power_state)
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{
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return tegra_soc_validate_power_state(power_state);
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}
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/*******************************************************************************
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* Handler called when an affinity instance is about to be turned on. The
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* level and mpidr determine the affinity instance.
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******************************************************************************/
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int tegra_affinst_on(unsigned long mpidr,
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unsigned long sec_entrypoint,
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unsigned int afflvl,
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unsigned int state)
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int tegra_pwr_domain_on(u_register_t mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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/*
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* Support individual CPU power on only.
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*/
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if (afflvl > MPIDR_AFFLVL0)
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return PSCI_E_SUCCESS;
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/*
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* Flush entrypoint variable to PoC since it will be
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* accessed after a reset with the caches turned off.
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*/
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sec_entry_point[cpu] = sec_entrypoint;
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flush_dcache_range((uint64_t)&sec_entry_point[cpu], sizeof(uint64_t));
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return tegra_soc_prepare_cpu_on(mpidr);
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return tegra_soc_pwr_domain_on(mpidr);
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}
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/*******************************************************************************
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* Handler called when an affinity instance is about to be turned off. The
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* level determines the affinity instance. The 'state' arg. allows the
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* platform to decide whether the cluster is being turned off and take apt
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* actions.
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*
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* CAUTION: This function is called with coherent stacks so that caches can be
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* turned off, flushed and coherency disabled. There is no guarantee that caches
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* will remain turned on across calls to this function as each affinity level is
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* dealt with. So do not write & read global variables across calls. It will be
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* wise to do flush a write to the global to prevent unpredictable results.
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* Handler called when a power domain is about to be turned off. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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void tegra_affinst_off(unsigned int afflvl, unsigned int state)
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void tegra_pwr_domain_off(const psci_power_state_t *target_state)
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{
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/*
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* Support individual CPU power off only.
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*/
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if (afflvl > MPIDR_AFFLVL0)
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return;
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tegra_soc_prepare_cpu_off(read_mpidr());
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tegra_soc_pwr_domain_off(target_state);
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}
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/*******************************************************************************
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* Handler called when an affinity instance is about to be suspended. The
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* level and mpidr determine the affinity instance. The 'state' arg. allows the
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* platform to decide whether the cluster is being turned off and take apt
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* actions.
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*
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* CAUTION: This function is called with coherent stacks so that caches can be
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* turned off, flushed and coherency disabled. There is no guarantee that caches
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* will remain turned on across calls to this function as each affinity level is
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* dealt with. So do not write & read global variables across calls. It will be
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* wise to flush a write to the global variable, to prevent unpredictable
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* results.
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* Handler called when called when a power domain is about to be suspended. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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void tegra_affinst_suspend(unsigned long sec_entrypoint,
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unsigned int afflvl,
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unsigned int state)
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void tegra_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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int id = psci_get_suspend_stateid();
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int cpu = read_mpidr() & MPIDR_CPU_MASK;
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if (afflvl > PLATFORM_MAX_AFFLVL)
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return;
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/*
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* Flush entrypoint variable to PoC since it will be
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* accessed after a reset with the caches turned off.
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*/
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sec_entry_point[cpu] = sec_entrypoint;
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flush_dcache_range((uint64_t)&sec_entry_point[cpu], sizeof(uint64_t));
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tegra_soc_prepare_cpu_suspend(id, afflvl);
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tegra_soc_pwr_domain_suspend(target_state);
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/* disable GICC */
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tegra_gic_cpuif_deactivate();
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}
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/*******************************************************************************
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* Handler called when an affinity instance has just been powered on after
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* being turned off earlier. The level determines the affinity instance.
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* The 'state' arg. allows the platform to decide whether the cluster was
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* turned off prior to wakeup and do what's necessary to set it up.
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* Handler called when a power domain has just been powered on after
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* being turned off earlier. The target_state encodes the low power state that
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* each level has woken up from.
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******************************************************************************/
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void tegra_affinst_on_finish(unsigned int afflvl, unsigned int state)
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void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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plat_params_from_bl2_t *plat_params;
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/*
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* Support individual CPU power on only.
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*/
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if (afflvl > MPIDR_AFFLVL0)
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return;
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/*
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* Initialize the GIC cpu and distributor interfaces
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*/
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@ -253,7 +157,8 @@ void tegra_affinst_on_finish(unsigned int afflvl, unsigned int state)
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/*
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* Check if we are exiting from deep sleep.
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*/
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if (tegra_system_suspended()) {
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if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
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PSTATE_ID_SOC_POWERDN) {
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/*
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* Lock scratch registers which hold the CPU vectors.
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|
@ -276,18 +181,17 @@ void tegra_affinst_on_finish(unsigned int afflvl, unsigned int state)
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/*
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* Reset hardware settings.
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*/
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tegra_soc_prepare_cpu_on_finish(read_mpidr());
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tegra_soc_pwr_domain_on_finish(target_state);
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}
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/*******************************************************************************
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* Handler called when an affinity instance has just been powered on after
|
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* having been suspended earlier. The level and mpidr determine the affinity
|
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* instance.
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* Handler called when a power domain has just been powered on after
|
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* having been suspended earlier. The target_state encodes the low power state
|
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* that each level has woken up from.
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******************************************************************************/
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void tegra_affinst_suspend_finish(unsigned int afflvl, unsigned int state)
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void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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if (afflvl == MPIDR_AFFLVL0)
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tegra_affinst_on_finish(afflvl, state);
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tegra_pwr_domain_on_finish(target_state);
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}
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/*******************************************************************************
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||||
|
@ -313,36 +217,78 @@ __dead2 void tegra_system_reset(void)
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tegra_pmc_system_reset();
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}
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|
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/*******************************************************************************
|
||||
* Handler called to check the validity of the power state parameter.
|
||||
******************************************************************************/
|
||||
int32_t tegra_validate_power_state(unsigned int power_state,
|
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psci_power_state_t *req_state)
|
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{
|
||||
int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
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||||
|
||||
assert(req_state);
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||||
|
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if (pwr_lvl > PLAT_MAX_PWR_LVL)
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return PSCI_E_INVALID_PARAMS;
|
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|
||||
return tegra_soc_validate_power_state(power_state, req_state);
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||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform handler called to check the validity of the non secure entrypoint.
|
||||
******************************************************************************/
|
||||
int tegra_validate_ns_entrypoint(uintptr_t entrypoint)
|
||||
{
|
||||
/*
|
||||
* Check if the non secure entrypoint lies within the non
|
||||
* secure DRAM.
|
||||
*/
|
||||
if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END))
|
||||
return PSCI_E_SUCCESS;
|
||||
|
||||
return PSCI_E_INVALID_ADDRESS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Export the platform handlers to enable psci to invoke them
|
||||
******************************************************************************/
|
||||
static const plat_pm_ops_t tegra_plat_pm_ops = {
|
||||
.affinst_standby = tegra_affinst_standby,
|
||||
.affinst_on = tegra_affinst_on,
|
||||
.affinst_off = tegra_affinst_off,
|
||||
.affinst_suspend = tegra_affinst_suspend,
|
||||
.affinst_on_finish = tegra_affinst_on_finish,
|
||||
.affinst_suspend_finish = tegra_affinst_suspend_finish,
|
||||
.system_off = tegra_system_off,
|
||||
.system_reset = tegra_system_reset,
|
||||
.validate_power_state = tegra_validate_power_state,
|
||||
.get_sys_suspend_power_state = tegra_get_sys_suspend_power_state
|
||||
static const plat_psci_ops_t tegra_plat_psci_ops = {
|
||||
.cpu_standby = tegra_cpu_standby,
|
||||
.pwr_domain_on = tegra_pwr_domain_on,
|
||||
.pwr_domain_off = tegra_pwr_domain_off,
|
||||
.pwr_domain_suspend = tegra_pwr_domain_suspend,
|
||||
.pwr_domain_on_finish = tegra_pwr_domain_on_finish,
|
||||
.pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish,
|
||||
.system_off = tegra_system_off,
|
||||
.system_reset = tegra_system_reset,
|
||||
.validate_power_state = tegra_validate_power_state,
|
||||
.validate_ns_entrypoint = tegra_validate_ns_entrypoint,
|
||||
.get_sys_suspend_power_state = tegra_get_sys_suspend_power_state,
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Export the platform specific power ops & initialize the fvp power controller
|
||||
* Export the platform specific power ops and initialize Power Controller
|
||||
******************************************************************************/
|
||||
int platform_setup_pm(const plat_pm_ops_t **plat_ops)
|
||||
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
||||
const plat_psci_ops_t **psci_ops)
|
||||
{
|
||||
psci_power_state_t target_state = { { PSCI_LOCAL_STATE_RUN } };
|
||||
|
||||
/*
|
||||
* Flush entrypoint variable to PoC since it will be
|
||||
* accessed after a reset with the caches turned off.
|
||||
*/
|
||||
tegra_sec_entry_point = sec_entrypoint;
|
||||
flush_dcache_range((uint64_t)&tegra_sec_entry_point, sizeof(uint64_t));
|
||||
|
||||
/*
|
||||
* Reset hardware settings.
|
||||
*/
|
||||
tegra_soc_prepare_cpu_on_finish(read_mpidr());
|
||||
tegra_soc_pwr_domain_on_finish(&target_state);
|
||||
|
||||
/*
|
||||
* Initialize PM ops struct
|
||||
* Initialize PSCI ops struct
|
||||
*/
|
||||
*plat_ops = &tegra_plat_pm_ops;
|
||||
*psci_ops = &tegra_plat_psci_ops;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -28,45 +28,47 @@
|
|||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <arch.h>
|
||||
#include <platform_def.h>
|
||||
#include <psci.h>
|
||||
|
||||
extern const unsigned char tegra_power_domain_tree_desc[];
|
||||
|
||||
/*******************************************************************************
|
||||
* This function implements a part of the critical interface between the psci
|
||||
* generic layer and the platform to allow the former to detect the platform
|
||||
* topology. psci queries the platform to determine how many affinity instances
|
||||
* are present at a particular level for a given mpidr.
|
||||
* This function returns the Tegra default topology tree information.
|
||||
******************************************************************************/
|
||||
unsigned int plat_get_aff_count(unsigned int aff_lvl,
|
||||
unsigned long mpidr)
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
{
|
||||
switch (aff_lvl) {
|
||||
case MPIDR_AFFLVL2:
|
||||
/* Last supported affinity level */
|
||||
return 1;
|
||||
|
||||
case MPIDR_AFFLVL1:
|
||||
/* Return # of clusters */
|
||||
return PLATFORM_CLUSTER_COUNT;
|
||||
|
||||
case MPIDR_AFFLVL0:
|
||||
/* # of cpus per cluster */
|
||||
return PLATFORM_MAX_CPUS_PER_CLUSTER;
|
||||
|
||||
default:
|
||||
return PSCI_AFF_ABSENT;
|
||||
}
|
||||
return tegra_power_domain_tree_desc;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function implements a part of the critical interface between the psci
|
||||
* generic layer and the platform to allow the former to detect the state of a
|
||||
* affinity instance in the platform topology. psci queries the platform to
|
||||
* determine whether an affinity instance is present or absent.
|
||||
* generic layer and the platform that allows the former to query the platform
|
||||
* to convert an MPIDR to a unique linear index. An error code (-1) is returned
|
||||
* in case the MPIDR is invalid.
|
||||
******************************************************************************/
|
||||
unsigned int plat_get_aff_state(unsigned int aff_lvl,
|
||||
unsigned long mpidr)
|
||||
int plat_core_pos_by_mpidr(u_register_t mpidr)
|
||||
{
|
||||
return (aff_lvl <= MPIDR_AFFLVL2) ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT;
|
||||
unsigned int cluster_id, cpu_id;
|
||||
|
||||
mpidr &= MPIDR_AFFINITY_MASK;
|
||||
|
||||
if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
|
||||
return -1;
|
||||
|
||||
cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
|
||||
cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
|
||||
|
||||
if (cluster_id >= PLATFORM_CLUSTER_COUNT)
|
||||
return -1;
|
||||
|
||||
/*
|
||||
* Validate cpu_id by checking whether it represents a CPU in
|
||||
* one of the two clusters present on the platform.
|
||||
*/
|
||||
if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
|
||||
return -1;
|
||||
|
||||
return (cpu_id + (cluster_id * 4));
|
||||
}
|
||||
|
|
|
@ -73,8 +73,8 @@ static inline void tegra_fc_write_32(uint32_t off, uint32_t val)
|
|||
mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val);
|
||||
}
|
||||
|
||||
void tegra_fc_cpu_idle(uint32_t mpidr);
|
||||
void tegra_fc_cluster_idle(uint32_t midr);
|
||||
void tegra_fc_cpu_powerdn(uint32_t mpidr);
|
||||
void tegra_fc_cluster_powerdn(uint32_t midr);
|
||||
void tegra_fc_soc_powerdn(uint32_t midr);
|
||||
void tegra_fc_cpu_on(int cpu);
|
||||
|
|
|
@ -33,6 +33,7 @@
|
|||
|
||||
#include <arch.h>
|
||||
#include <common_def.h>
|
||||
#include <tegra_def.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Generic platform constants
|
||||
|
@ -47,12 +48,18 @@
|
|||
|
||||
#define TEGRA_PRIMARY_CPU 0x0
|
||||
|
||||
#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
|
||||
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
|
||||
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
|
||||
PLATFORM_MAX_CPUS_PER_CLUSTER)
|
||||
#define PLATFORM_NUM_AFFS (PLATFORM_CORE_COUNT + \
|
||||
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
|
||||
PLATFORM_CLUSTER_COUNT + 1)
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform power states
|
||||
******************************************************************************/
|
||||
#define PLAT_MAX_RET_STATE 1
|
||||
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1)
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform console related constants
|
||||
******************************************************************************/
|
||||
|
|
|
@ -37,7 +37,7 @@
|
|||
* This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
|
||||
* call as the `state-id` field in the 'power state' parameter.
|
||||
******************************************************************************/
|
||||
#define PLAT_SYS_SUSPEND_STATE_ID 0xD
|
||||
#define PSTATE_ID_SOC_POWERDN 0xD
|
||||
|
||||
/*******************************************************************************
|
||||
* GIC memory map
|
||||
|
|
|
@ -31,8 +31,9 @@
|
|||
#ifndef __TEGRA_PRIVATE_H__
|
||||
#define __TEGRA_PRIVATE_H__
|
||||
|
||||
#include <xlat_tables.h>
|
||||
#include <arch.h>
|
||||
#include <platform_def.h>
|
||||
#include <xlat_tables.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Tegra DRAM memory base address
|
||||
|
@ -45,7 +46,8 @@ typedef struct plat_params_from_bl2 {
|
|||
} plat_params_from_bl2_t;
|
||||
|
||||
/* Declarations for plat_psci_handlers.c */
|
||||
int32_t tegra_soc_validate_power_state(unsigned int power_state);
|
||||
int32_t tegra_soc_validate_power_state(unsigned int power_state,
|
||||
psci_power_state_t *req_state);
|
||||
|
||||
/* Declarations for plat_setup.c */
|
||||
const mmap_region_t *plat_get_mmio_map(void);
|
||||
|
|
|
@ -28,7 +28,10 @@
|
|||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
|
||||
SOC_DIR := plat/nvidia/tegra/soc/${TARGET_SOC}
|
||||
SOC_DIR := plat/nvidia/tegra/soc/${TARGET_SOC}
|
||||
|
||||
# Disable the PSCI platform compatibility layer
|
||||
ENABLE_PLAT_COMPAT := 0
|
||||
|
||||
include plat/nvidia/tegra/common/tegra_common.mk
|
||||
include ${SOC_DIR}/platform_${TARGET_SOC}.mk
|
||||
|
|
|
@ -56,28 +56,55 @@
|
|||
|
||||
static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
|
||||
|
||||
int32_t tegra_soc_validate_power_state(unsigned int power_state)
|
||||
int32_t tegra_soc_validate_power_state(unsigned int power_state,
|
||||
psci_power_state_t *req_state)
|
||||
{
|
||||
int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
|
||||
int state_id = psci_get_pstate_id(power_state);
|
||||
int cpu = read_mpidr() & MPIDR_CPU_MASK;
|
||||
|
||||
if (pwr_lvl > PLAT_MAX_PWR_LVL)
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
|
||||
/* Sanity check the requested afflvl */
|
||||
if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) {
|
||||
/*
|
||||
* It's possible to enter standby only on affinity level 0 i.e.
|
||||
* a cpu on Tegra. Ignore any other affinity level.
|
||||
*/
|
||||
if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0)
|
||||
if (pwr_lvl != MPIDR_AFFLVL0)
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
|
||||
/* power domain in standby state */
|
||||
req_state->pwr_domain_state[pwr_lvl] = PLAT_MAX_RET_STATE;
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
/* Sanity check the requested state id */
|
||||
if (psci_get_pstate_id(power_state) != PLAT_SYS_SUSPEND_STATE_ID) {
|
||||
ERROR("unsupported state id\n");
|
||||
return PSCI_E_NOT_SUPPORTED;
|
||||
/*
|
||||
* Sanity check the requested state id, power level and CPU number.
|
||||
* Currently T132 only supports SYSTEM_SUSPEND on last standing CPU
|
||||
* i.e. CPU 0
|
||||
*/
|
||||
if ((pwr_lvl != PLAT_MAX_PWR_LVL) ||
|
||||
(state_id != PSTATE_ID_SOC_POWERDN) ||
|
||||
(cpu != 0)) {
|
||||
ERROR("unsupported state id @ power level\n");
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
}
|
||||
|
||||
/* Set lower power states to PLAT_MAX_OFF_STATE */
|
||||
for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
|
||||
req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
|
||||
|
||||
/* Set the SYSTEM_SUSPEND state-id */
|
||||
req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] =
|
||||
PSTATE_ID_SOC_POWERDN;
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
int tegra_soc_prepare_cpu_on(unsigned long mpidr)
|
||||
int tegra_soc_pwr_domain_on(u_register_t mpidr)
|
||||
{
|
||||
int cpu = mpidr & MPIDR_CPU_MASK;
|
||||
uint32_t mask = CPU_CORE_RESET_MASK << cpu;
|
||||
|
@ -101,29 +128,29 @@ int tegra_soc_prepare_cpu_on(unsigned long mpidr)
|
|||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
int tegra_soc_prepare_cpu_off(unsigned long mpidr)
|
||||
int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
|
||||
{
|
||||
tegra_fc_cpu_off(mpidr & MPIDR_CPU_MASK);
|
||||
tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
int tegra_soc_prepare_cpu_suspend(unsigned int id, unsigned int afflvl)
|
||||
int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
|
||||
{
|
||||
/* Nothing to be done for lower affinity levels */
|
||||
if (afflvl < MPIDR_AFFLVL2)
|
||||
return PSCI_E_SUCCESS;
|
||||
#if DEBUG
|
||||
int cpu = read_mpidr() & MPIDR_CPU_MASK;
|
||||
|
||||
/* Enter system suspend state */
|
||||
tegra_pm_system_suspend_entry();
|
||||
/* SYSTEM_SUSPEND only on CPU0 */
|
||||
assert(cpu == 0);
|
||||
#endif
|
||||
|
||||
/* Allow restarting CPU #1 using PMC on suspend exit */
|
||||
cpu_powergate_mask[1] = 0;
|
||||
|
||||
/* Program FC to enter suspend state */
|
||||
tegra_fc_cpu_idle(read_mpidr());
|
||||
tegra_fc_cpu_powerdn(read_mpidr());
|
||||
|
||||
/* Suspend DCO operations */
|
||||
write_actlr_el1(id);
|
||||
write_actlr_el1(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]);
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
|
|
@ -31,6 +31,21 @@
|
|||
#include <xlat_tables.h>
|
||||
#include <tegra_def.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* The Tegra power domain tree has a single system level power domain i.e. a
|
||||
* single root node. The first entry in the power domain descriptor specifies
|
||||
* the number of power domains at the highest power level.
|
||||
*******************************************************************************
|
||||
*/
|
||||
const unsigned char tegra_power_domain_tree_desc[] = {
|
||||
/* No of root nodes */
|
||||
1,
|
||||
/* No of clusters */
|
||||
PLATFORM_CLUSTER_COUNT,
|
||||
/* No of CPU cores */
|
||||
PLATFORM_CORE_COUNT,
|
||||
};
|
||||
|
||||
/* sets of MMIO ranges setup */
|
||||
#define MMIO_RANGE_0_ADDR 0x50000000
|
||||
#define MMIO_RANGE_1_ADDR 0x60000000
|
||||
|
|
|
@ -55,83 +55,139 @@
|
|||
|
||||
static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
|
||||
|
||||
int32_t tegra_soc_validate_power_state(unsigned int power_state)
|
||||
int32_t tegra_soc_validate_power_state(unsigned int power_state,
|
||||
psci_power_state_t *req_state)
|
||||
{
|
||||
int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
|
||||
int state_id = psci_get_pstate_id(power_state);
|
||||
|
||||
if (pwr_lvl > PLAT_MAX_PWR_LVL) {
|
||||
ERROR("%s: unsupported power_state (0x%x)\n", __func__,
|
||||
power_state);
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
}
|
||||
|
||||
/* Sanity check the requested afflvl */
|
||||
if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) {
|
||||
/*
|
||||
* It's possible to enter standby only on affinity level 0 i.e.
|
||||
* a cpu on Tegra. Ignore any other affinity level.
|
||||
*/
|
||||
if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0)
|
||||
if (pwr_lvl != MPIDR_AFFLVL0)
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
|
||||
/* power domain in standby state */
|
||||
req_state->pwr_domain_state[pwr_lvl] = PLAT_MAX_RET_STATE;
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
/* Sanity check the requested state id */
|
||||
switch (psci_get_pstate_id(power_state)) {
|
||||
switch (state_id) {
|
||||
case PSTATE_ID_CORE_POWERDN:
|
||||
/*
|
||||
* Core powerdown request only for afflvl 0
|
||||
*/
|
||||
if (pwr_lvl != MPIDR_AFFLVL0)
|
||||
goto error;
|
||||
|
||||
req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff;
|
||||
|
||||
break;
|
||||
|
||||
case PSTATE_ID_CLUSTER_IDLE:
|
||||
case PSTATE_ID_CLUSTER_POWERDN:
|
||||
/*
|
||||
* Cluster powerdown/idle request only for afflvl 1
|
||||
*/
|
||||
if (pwr_lvl != MPIDR_AFFLVL1)
|
||||
goto error;
|
||||
|
||||
req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id;
|
||||
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
|
||||
|
||||
break;
|
||||
|
||||
case PSTATE_ID_SOC_POWERDN:
|
||||
/*
|
||||
* System powerdown request only for afflvl 2
|
||||
*/
|
||||
if (pwr_lvl != PLAT_MAX_PWR_LVL)
|
||||
goto error;
|
||||
|
||||
for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
|
||||
req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
|
||||
|
||||
req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] =
|
||||
PLAT_SYS_SUSPEND_STATE_ID;
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
ERROR("unsupported state id\n");
|
||||
ERROR("%s: unsupported state id (%d)\n", __func__, state_id);
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
}
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
|
||||
error:
|
||||
ERROR("%s: unsupported state id (%d)\n", __func__, state_id);
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
}
|
||||
|
||||
int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
|
||||
{
|
||||
u_register_t mpidr = read_mpidr();
|
||||
const plat_local_state_t *pwr_domain_state =
|
||||
target_state->pwr_domain_state;
|
||||
unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2];
|
||||
unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1];
|
||||
unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0];
|
||||
|
||||
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
|
||||
|
||||
assert(stateid_afflvl0 == PLAT_MAX_OFF_STATE);
|
||||
assert(stateid_afflvl1 == PLAT_MAX_OFF_STATE);
|
||||
|
||||
/* suspend the entire soc */
|
||||
tegra_fc_soc_powerdn(mpidr);
|
||||
|
||||
} else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) {
|
||||
|
||||
assert(stateid_afflvl0 == PLAT_MAX_OFF_STATE);
|
||||
|
||||
/* Prepare for cluster idle */
|
||||
tegra_fc_cluster_idle(mpidr);
|
||||
|
||||
} else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_POWERDN) {
|
||||
|
||||
assert(stateid_afflvl0 == PLAT_MAX_OFF_STATE);
|
||||
|
||||
/* Prepare for cluster powerdn */
|
||||
tegra_fc_cluster_powerdn(mpidr);
|
||||
|
||||
} else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) {
|
||||
|
||||
/* Prepare for cpu powerdn */
|
||||
tegra_fc_cpu_powerdn(mpidr);
|
||||
|
||||
} else {
|
||||
ERROR("%s: Unknown state id\n", __func__);
|
||||
return PSCI_E_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
int tegra_soc_prepare_cpu_suspend(unsigned int id, unsigned int afflvl)
|
||||
{
|
||||
/* There's nothing to be done for affinity level 1 */
|
||||
if (afflvl == MPIDR_AFFLVL1)
|
||||
return PSCI_E_SUCCESS;
|
||||
|
||||
switch (id) {
|
||||
/* Prepare for cpu idle */
|
||||
case PSTATE_ID_CORE_POWERDN:
|
||||
tegra_fc_cpu_idle(read_mpidr());
|
||||
return PSCI_E_SUCCESS;
|
||||
|
||||
/* Prepare for cluster idle */
|
||||
case PSTATE_ID_CLUSTER_IDLE:
|
||||
tegra_fc_cluster_idle(read_mpidr());
|
||||
return PSCI_E_SUCCESS;
|
||||
|
||||
/* Prepare for cluster powerdn */
|
||||
case PSTATE_ID_CLUSTER_POWERDN:
|
||||
tegra_fc_cluster_powerdn(read_mpidr());
|
||||
return PSCI_E_SUCCESS;
|
||||
|
||||
/* Prepare for system idle */
|
||||
case PSTATE_ID_SOC_POWERDN:
|
||||
|
||||
/* Enter system suspend state */
|
||||
tegra_pm_system_suspend_entry();
|
||||
|
||||
/* suspend the entire soc */
|
||||
tegra_fc_soc_powerdn(read_mpidr());
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
|
||||
default:
|
||||
ERROR("Unknown state id (%d)\n", id);
|
||||
break;
|
||||
}
|
||||
|
||||
return PSCI_E_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
int tegra_soc_prepare_cpu_on_finish(unsigned long mpidr)
|
||||
int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
/*
|
||||
* Check if we are exiting from SOC_POWERDN.
|
||||
*/
|
||||
if (tegra_system_suspended()) {
|
||||
if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
|
||||
PLAT_SYS_SUSPEND_STATE_ID) {
|
||||
|
||||
/*
|
||||
* Enable WRAP to INCR burst type conversions for
|
||||
|
@ -147,11 +203,6 @@ int tegra_soc_prepare_cpu_on_finish(unsigned long mpidr)
|
|||
* address and reset it.
|
||||
*/
|
||||
tegra_fc_reset_bpmp();
|
||||
|
||||
/*
|
||||
* System resume complete.
|
||||
*/
|
||||
tegra_pm_system_suspend_exit();
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -159,13 +210,12 @@ int tegra_soc_prepare_cpu_on_finish(unsigned long mpidr)
|
|||
* used for power management and boot purposes. Inform the BPMP that
|
||||
* we have completed the cluster power up.
|
||||
*/
|
||||
if (psci_get_max_phys_off_afflvl() == MPIDR_AFFLVL1)
|
||||
tegra_fc_lock_active_cluster();
|
||||
tegra_fc_lock_active_cluster();
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
int tegra_soc_prepare_cpu_on(unsigned long mpidr)
|
||||
int tegra_soc_pwr_domain_on(u_register_t mpidr)
|
||||
{
|
||||
int cpu = mpidr & MPIDR_CPU_MASK;
|
||||
uint32_t mask = CPU_CORE_RESET_MASK << cpu;
|
||||
|
@ -184,9 +234,9 @@ int tegra_soc_prepare_cpu_on(unsigned long mpidr)
|
|||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
int tegra_soc_prepare_cpu_off(unsigned long mpidr)
|
||||
int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
|
||||
{
|
||||
tegra_fc_cpu_off(mpidr & MPIDR_CPU_MASK);
|
||||
tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
|
|
|
@ -32,6 +32,23 @@
|
|||
#include <tegra_def.h>
|
||||
#include <xlat_tables.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* The Tegra power domain tree has a single system level power domain i.e. a
|
||||
* single root node. The first entry in the power domain descriptor specifies
|
||||
* the number of power domains at the highest power level.
|
||||
*******************************************************************************
|
||||
*/
|
||||
const unsigned char tegra_power_domain_tree_desc[] = {
|
||||
/* No of root nodes */
|
||||
1,
|
||||
/* No of clusters */
|
||||
PLATFORM_CLUSTER_COUNT,
|
||||
/* No of CPU cores - cluster0 */
|
||||
PLATFORM_MAX_CPUS_PER_CLUSTER,
|
||||
/* No of CPU cores - cluster1 */
|
||||
PLATFORM_MAX_CPUS_PER_CLUSTER
|
||||
};
|
||||
|
||||
/* sets of MMIO ranges setup */
|
||||
#define MMIO_RANGE_0_ADDR 0x50000000
|
||||
#define MMIO_RANGE_1_ADDR 0x60000000
|
||||
|
|
Loading…
Reference in New Issue