Add SPI-MEM framework
This framework supports SPI operations using a common spi_mem_op structure: - command - addr - dummy - data The framework manages SPI bus configuration: - speed - bus width (Up to quad mode) - chip select Change-Id: Idc2736c59bfc5ac6e55429eba5d385275ea3fbde Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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Lionel Debieve
parent
b114abb609
commit
05e6a5638b
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/*
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* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <libfdt.h>
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#include <drivers/spi_mem.h>
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#include <lib/utils_def.h>
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#define SPI_MEM_DEFAULT_SPEED_HZ 100000U
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/*
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* struct spi_slave - Representation of a SPI slave.
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*
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* @max_hz: Maximum speed for this slave in Hertz.
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* @cs: ID of the chip select connected to the slave.
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* @mode: SPI mode to use for this slave (see SPI mode flags).
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* @ops: Ops defined by the bus.
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*/
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struct spi_slave {
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unsigned int max_hz;
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unsigned int cs;
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unsigned int mode;
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const struct spi_bus_ops *ops;
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};
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static struct spi_slave spi_slave;
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static bool spi_mem_check_buswidth_req(uint8_t buswidth, bool tx)
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{
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switch (buswidth) {
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case 1U:
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return true;
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case 2U:
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if ((tx && (spi_slave.mode & (SPI_TX_DUAL | SPI_TX_QUAD)) !=
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0U) ||
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(!tx && (spi_slave.mode & (SPI_RX_DUAL | SPI_RX_QUAD)) !=
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0U)) {
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return true;
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}
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break;
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case 4U:
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if ((tx && (spi_slave.mode & SPI_TX_QUAD) != 0U) ||
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(!tx && (spi_slave.mode & SPI_RX_QUAD) != 0U)) {
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return true;
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}
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break;
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default:
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break;
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}
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return false;
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}
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static bool spi_mem_supports_op(const struct spi_mem_op *op)
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{
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if (!spi_mem_check_buswidth_req(op->cmd.buswidth, true)) {
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return false;
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}
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if ((op->addr.nbytes != 0U) &&
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!spi_mem_check_buswidth_req(op->addr.buswidth, true)) {
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return false;
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}
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if ((op->dummy.nbytes != 0U) &&
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!spi_mem_check_buswidth_req(op->dummy.buswidth, true)) {
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return false;
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}
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if ((op->data.nbytes != 0U) &&
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!spi_mem_check_buswidth_req(op->data.buswidth,
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op->data.dir == SPI_MEM_DATA_OUT)) {
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return false;
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}
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return true;
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}
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static int spi_mem_set_speed_mode(void)
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{
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const struct spi_bus_ops *ops = spi_slave.ops;
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int ret;
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ret = ops->set_speed(spi_slave.max_hz);
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if (ret != 0) {
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VERBOSE("Cannot set speed (err=%d)\n", ret);
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return ret;
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}
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ret = ops->set_mode(spi_slave.mode);
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if (ret != 0) {
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VERBOSE("Cannot set mode (err=%d)\n", ret);
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return ret;
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}
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return 0;
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}
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static int spi_mem_check_bus_ops(const struct spi_bus_ops *ops)
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{
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bool error = false;
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if (ops->claim_bus == NULL) {
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VERBOSE("Ops claim bus is not defined\n");
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error = true;
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}
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if (ops->release_bus == NULL) {
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VERBOSE("Ops release bus is not defined\n");
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error = true;
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}
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if (ops->exec_op == NULL) {
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VERBOSE("Ops exec op is not defined\n");
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error = true;
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}
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if (ops->set_speed == NULL) {
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VERBOSE("Ops set speed is not defined\n");
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error = true;
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}
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if (ops->set_mode == NULL) {
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VERBOSE("Ops set mode is not defined\n");
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error = true;
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}
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return error ? -EINVAL : 0;
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}
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/*
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* spi_mem_exec_op() - Execute a memory operation.
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* @op: The memory operation to execute.
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*
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* This function first checks that @op is supported and then tries to execute
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* it.
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*
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* Return: 0 in case of success, a negative error code otherwise.
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*/
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int spi_mem_exec_op(const struct spi_mem_op *op)
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{
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const struct spi_bus_ops *ops = spi_slave.ops;
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int ret;
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VERBOSE("%s: cmd:%x mode:%d.%d.%d.%d addqr:%llx len:%x\n",
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__func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
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op->dummy.buswidth, op->data.buswidth,
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op->addr.val, op->data.nbytes);
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if (!spi_mem_supports_op(op)) {
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WARN("Error in spi_mem_support\n");
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return -ENOTSUP;
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}
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ret = ops->claim_bus(spi_slave.cs);
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if (ret != 0) {
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WARN("Error claim_bus\n");
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return ret;
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}
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ret = ops->exec_op(op);
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ops->release_bus();
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return ret;
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}
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/*
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* spi_mem_init_slave() - SPI slave device initialization.
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* @fdt: Pointer to the device tree blob.
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* @bus_node: Offset of the bus node.
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* @ops: The SPI bus ops defined.
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*
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* This function first checks that @ops are supported and then tries to find
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* a SPI slave device.
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*
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* Return: 0 in case of success, a negative error code otherwise.
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*/
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int spi_mem_init_slave(void *fdt, int bus_node, const struct spi_bus_ops *ops)
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{
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int ret;
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int mode = 0;
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int nchips = 0;
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int bus_subnode = 0;
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const fdt32_t *cuint = NULL;
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ret = spi_mem_check_bus_ops(ops);
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if (ret != 0) {
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return ret;
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}
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fdt_for_each_subnode(bus_subnode, fdt, bus_node) {
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nchips++;
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}
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if (nchips != 1) {
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ERROR("Only one SPI device is currently supported\n");
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return -EINVAL;
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}
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fdt_for_each_subnode(bus_subnode, fdt, bus_node) {
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/* Get chip select */
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cuint = fdt_getprop(fdt, bus_subnode, "reg", NULL);
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if (cuint == NULL) {
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ERROR("Chip select not well defined\n");
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return -EINVAL;
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}
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spi_slave.cs = fdt32_to_cpu(*cuint);
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/* Get max slave frequency */
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spi_slave.max_hz = SPI_MEM_DEFAULT_SPEED_HZ;
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cuint = fdt_getprop(fdt, bus_subnode,
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"spi-max-frequency", NULL);
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if (cuint != NULL) {
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spi_slave.max_hz = fdt32_to_cpu(*cuint);
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}
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/* Get mode */
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if ((fdt_getprop(fdt, bus_subnode, "spi-cpol", NULL)) != NULL) {
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mode |= SPI_CPOL;
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}
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if ((fdt_getprop(fdt, bus_subnode, "spi-cpha", NULL)) != NULL) {
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mode |= SPI_CPHA;
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}
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if ((fdt_getprop(fdt, bus_subnode, "spi-cs-high", NULL)) !=
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NULL) {
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mode |= SPI_CS_HIGH;
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}
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if ((fdt_getprop(fdt, bus_subnode, "spi-3wire", NULL)) !=
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NULL) {
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mode |= SPI_3WIRE;
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}
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if ((fdt_getprop(fdt, bus_subnode, "spi-half-duplex", NULL)) !=
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NULL) {
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mode |= SPI_PREAMBLE;
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}
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/* Get dual/quad mode */
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cuint = fdt_getprop(fdt, bus_subnode, "spi-tx-bus-width", NULL);
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if (cuint != NULL) {
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switch (fdt32_to_cpu(*cuint)) {
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case 1U:
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break;
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case 2U:
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mode |= SPI_TX_DUAL;
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break;
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case 4U:
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mode |= SPI_TX_QUAD;
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break;
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default:
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WARN("spi-tx-bus-width %d not supported\n",
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fdt32_to_cpu(*cuint));
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return -EINVAL;
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}
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}
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cuint = fdt_getprop(fdt, bus_subnode, "spi-rx-bus-width", NULL);
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if (cuint != NULL) {
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switch (fdt32_to_cpu(*cuint)) {
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case 1U:
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break;
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case 2U:
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mode |= SPI_RX_DUAL;
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break;
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case 4U:
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mode |= SPI_RX_QUAD;
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break;
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default:
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WARN("spi-rx-bus-width %d not supported\n",
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fdt32_to_cpu(*cuint));
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return -EINVAL;
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}
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}
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spi_slave.mode = mode;
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spi_slave.ops = ops;
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}
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return spi_mem_set_speed_mode();
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}
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@ -0,0 +1,130 @@
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/*
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* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DRIVERS_SPI_MEM_H
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#define DRIVERS_SPI_MEM_H
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#include <errno.h>
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#include <stdbool.h>
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#include <stdint.h>
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#define SPI_MEM_BUSWIDTH_1_LINE 1U
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#define SPI_MEM_BUSWIDTH_2_LINE 2U
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#define SPI_MEM_BUSWIDTH_4_LINE 4U
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/*
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* enum spi_mem_data_dir - Describes the direction of a SPI memory data
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* transfer from the controller perspective.
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* @SPI_MEM_DATA_IN: data coming from the SPI memory.
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* @SPI_MEM_DATA_OUT: data sent to the SPI memory.
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*/
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enum spi_mem_data_dir {
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SPI_MEM_DATA_IN,
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SPI_MEM_DATA_OUT,
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};
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/*
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* struct spi_mem_op - Describes a SPI memory operation.
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*
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* @cmd.buswidth: Number of IO lines used to transmit the command.
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* @cmd.opcode: Operation opcode.
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* @addr.nbytes: Number of address bytes to send. Can be zero if the operation
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* does not need to send an address.
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* @addr.buswidth: Number of IO lines used to transmit the address.
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* @addr.val: Address value. This value is always sent MSB first on the bus.
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* Note that only @addr.nbytes are taken into account in this
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* address value, so users should make sure the value fits in the
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* assigned number of bytes.
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* @dummy.nbytes: Number of dummy bytes to send after an opcode or address. Can
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* be zero if the operation does not require dummy bytes.
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* @dummy.buswidth: Number of IO lines used to transmit the dummy bytes.
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* @data.buswidth: Number of IO lines used to send/receive the data.
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* @data.dir: Direction of the transfer.
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* @data.nbytes: Number of data bytes to transfer.
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* @data.buf: Input or output data buffer depending on data::dir.
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*/
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struct spi_mem_op {
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struct {
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uint8_t buswidth;
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uint8_t opcode;
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} cmd;
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struct {
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uint8_t nbytes;
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uint8_t buswidth;
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uint64_t val;
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} addr;
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struct {
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uint8_t nbytes;
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uint8_t buswidth;
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} dummy;
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struct {
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uint8_t buswidth;
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enum spi_mem_data_dir dir;
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unsigned int nbytes;
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void *buf;
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} data;
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};
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/* SPI mode flags */
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#define SPI_CPHA BIT(0) /* clock phase */
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#define SPI_CPOL BIT(1) /* clock polarity */
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#define SPI_CS_HIGH BIT(2) /* CS active high */
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#define SPI_LSB_FIRST BIT(3) /* per-word bits-on-wire */
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#define SPI_3WIRE BIT(4) /* SI/SO signals shared */
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#define SPI_PREAMBLE BIT(5) /* Skip preamble bytes */
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#define SPI_TX_DUAL BIT(6) /* transmit with 2 wires */
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#define SPI_TX_QUAD BIT(7) /* transmit with 4 wires */
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#define SPI_RX_DUAL BIT(8) /* receive with 2 wires */
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#define SPI_RX_QUAD BIT(9) /* receive with 4 wires */
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struct spi_bus_ops {
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/*
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* Claim the bus and prepare it for communication.
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*
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* @cs: The chip select.
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* Returns: 0 if the bus was claimed successfully, or a negative value
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* if it wasn't.
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*/
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int (*claim_bus)(unsigned int cs);
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/*
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* Release the SPI bus.
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*/
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void (*release_bus)(void);
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/*
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* Set transfer speed.
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*
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* @hz: The transfer speed in Hertz.
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* Returns: 0 on success, a negative error code otherwise.
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*/
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int (*set_speed)(unsigned int hz);
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/*
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* Set the SPI mode/flags.
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*
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* @mode: Requested SPI mode (SPI_... flags).
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* Returns: 0 on success, a negative error code otherwise.
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*/
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int (*set_mode)(unsigned int mode);
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/*
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* Execute a SPI memory operation.
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*
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* @op: The memory operation to execute.
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* Returns: 0 on success, a negative error code otherwise.
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*/
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int (*exec_op)(const struct spi_mem_op *op);
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};
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int spi_mem_exec_op(const struct spi_mem_op *op);
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int spi_mem_init_slave(void *fdt, int bus_node,
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const struct spi_bus_ops *ops);
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#endif /* DRIVERS_SPI_MEM_H */
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