Tegra186: split MCE driver into public/private interfaces
This patch splits the MCE driver into public and private interfaces to allow usage of common functionality across multiple SoCs. Change-Id: Ib58080e730d72f11ff79507d8e0acffb2ad5c606 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar
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45cd814bf7
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06060028e1
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MCE_H__
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#define __MCE_H__
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#include <mmio.h>
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#include <tegra_def.h>
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/*******************************************************************************
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* MCE commands
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******************************************************************************/
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typedef enum mce_cmd {
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MCE_CMD_ENTER_CSTATE = 0,
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MCE_CMD_UPDATE_CSTATE_INFO = 1,
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MCE_CMD_UPDATE_CROSSOVER_TIME = 2,
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MCE_CMD_READ_CSTATE_STATS = 3,
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MCE_CMD_WRITE_CSTATE_STATS = 4,
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MCE_CMD_IS_SC7_ALLOWED = 5,
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MCE_CMD_ONLINE_CORE = 6,
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MCE_CMD_CC3_CTRL = 7,
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MCE_CMD_ECHO_DATA = 8,
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MCE_CMD_READ_VERSIONS = 9,
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MCE_CMD_ENUM_FEATURES = 10,
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MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11,
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MCE_CMD_ENUM_READ_MCA = 12,
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MCE_CMD_ENUM_WRITE_MCA = 13,
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MCE_CMD_ROC_FLUSH_CACHE = 14,
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MCE_CMD_ROC_CLEAN_CACHE = 15,
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MCE_CMD_ENABLE_LATIC = 16,
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MCE_CMD_UNCORE_PERFMON_REQ = 17,
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MCE_CMD_MISC_CCPLEX = 18,
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MCE_CMD_IS_CCX_ALLOWED = 0xFE,
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MCE_CMD_MAX = 0xFF,
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} mce_cmd_t;
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#define MCE_CMD_MASK 0xFF
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/*******************************************************************************
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* Timeout value used to powerdown a core
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******************************************************************************/
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#define MCE_CORE_SLEEP_TIME_INFINITE 0xFFFFFFFF
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/*******************************************************************************
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* Struct to prepare UPDATE_CSTATE_INFO request
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******************************************************************************/
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typedef struct mce_cstate_info {
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/* cluster cstate value */
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uint32_t cluster;
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/* ccplex cstate value */
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uint32_t ccplex;
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/* system cstate value */
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uint32_t system;
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/* force system state? */
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uint8_t system_state_force;
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/* wake mask value */
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uint32_t wake_mask;
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/* update the wake mask? */
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uint8_t update_wake_mask;
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} mce_cstate_info_t;
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/* public interfaces */
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int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
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uint64_t arg2);
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int mce_update_reset_vector(void);
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int mce_update_gsc_videomem(void);
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int mce_update_gsc_tzdram(void);
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int mce_update_gsc_tzram(void);
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__dead2 void mce_enter_ccplex_state(uint32_t state_idx);
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void mce_update_cstate_info(mce_cstate_info_t *cstate);
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void mce_verify_firmware_version(void);
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#endif /* __MCE_H__ */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -28,59 +28,12 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MCE_H__
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#define __MCE_H__
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#ifndef __MCE_PRIVATE_H__
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#define __MCE_PRIVATE_H__
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#include <mmio.h>
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#include <tegra_def.h>
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/*******************************************************************************
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* MCE commands
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******************************************************************************/
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typedef enum mce_cmd {
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MCE_CMD_ENTER_CSTATE = 0,
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MCE_CMD_UPDATE_CSTATE_INFO = 1,
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MCE_CMD_UPDATE_CROSSOVER_TIME = 2,
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MCE_CMD_READ_CSTATE_STATS = 3,
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MCE_CMD_WRITE_CSTATE_STATS = 4,
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MCE_CMD_IS_SC7_ALLOWED = 5,
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MCE_CMD_ONLINE_CORE = 6,
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MCE_CMD_CC3_CTRL = 7,
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MCE_CMD_ECHO_DATA = 8,
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MCE_CMD_READ_VERSIONS = 9,
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MCE_CMD_ENUM_FEATURES = 10,
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MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11,
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MCE_CMD_ENUM_READ_MCA = 12,
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MCE_CMD_ENUM_WRITE_MCA = 13,
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MCE_CMD_ROC_FLUSH_CACHE = 14,
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MCE_CMD_ROC_CLEAN_CACHE = 15,
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MCE_CMD_ENABLE_LATIC = 16,
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MCE_CMD_UNCORE_PERFMON_REQ = 17,
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MCE_CMD_MISC_CCPLEX = 18,
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MCE_CMD_IS_CCX_ALLOWED = 0xFE,
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MCE_CMD_MAX = 0xFF,
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} mce_cmd_t;
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#define MCE_CMD_MASK 0xFF
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/*******************************************************************************
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* Struct to prepare UPDATE_CSTATE_INFO request
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******************************************************************************/
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typedef struct mce_cstate_info {
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/* cluster cstate value */
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uint32_t cluster;
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/* ccplex cstate value */
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uint32_t ccplex;
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/* system cstate value */
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uint32_t system;
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/* force system state? */
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uint8_t system_state_force;
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/* wake mask value */
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uint32_t wake_mask;
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/* update the wake mask? */
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uint8_t update_wake_mask;
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} mce_cstate_info_t;
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/*******************************************************************************
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* Macros to prepare CSTATE info request
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******************************************************************************/
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@ -126,11 +79,6 @@ typedef struct mce_cstate_info {
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******************************************************************************/
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#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32
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/*******************************************************************************
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* Timeout value used to powerdown a core
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******************************************************************************/
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#define MCE_CORE_SLEEP_TIME_INFINITE 0xFFFFFFFF
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/*******************************************************************************
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* MCA command struct
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******************************************************************************/
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@ -353,16 +301,6 @@ typedef struct arch_mce_ops {
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uint32_t value);
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} arch_mce_ops_t;
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int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
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uint64_t arg2);
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int mce_update_reset_vector(void);
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int mce_update_gsc_videomem(void);
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int mce_update_gsc_tzdram(void);
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int mce_update_gsc_tzram(void);
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__dead2 void mce_enter_ccplex_state(uint32_t state_idx);
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void mce_update_cstate_info(mce_cstate_info_t *cstate);
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void mce_verify_firmware_version(void);
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/* declarations for ARI/NVG handler functions */
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int ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
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int ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
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@ -399,4 +337,4 @@ int nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
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int nvg_online_core(uint32_t ari_base, uint32_t core);
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int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
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#endif /* __MCE_H__ */
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#endif /* __MCE_PRIVATE_H__ */
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@ -33,7 +33,7 @@
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#include <debug.h>
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#include <denver.h>
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#include <mmio.h>
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#include <mce.h>
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#include <mce_private.h>
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#include <sys/errno.h>
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#include <t18x_ari.h>
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#include <debug.h>
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#include <denver.h>
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#include <mce.h>
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#include <mce_private.h>
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#include <mmio.h>
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#include <string.h>
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#include <sys/errno.h>
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uint32_t major, minor;
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/*
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* MCE firmware is not running on simulation platforms.
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* MCE firmware is not supported on simulation platforms.
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*/
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if (tegra_platform_is_emulation())
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return;
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#include <debug.h>
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#include <denver.h>
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#include <mmio.h>
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#include <mce.h>
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#include <mce_private.h>
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#include <sys/errno.h>
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#include <t18x_ari.h>
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