stm32mp1: register shared resource per IOMEM address
Introduce helper functions stm32mp_register_secure_periph_iomem() and stm32mp_register_non_secure_periph_iomem() for drivers to register a resource as secure or non-secure based on its SoC interface registers base address. These functions are stubbed when shared resources driver is not embedded (!STM32MP_SHARED_RESOURCES) so that drivers embedded in other BL stages do not bother whether they shall register or not their resources. Change-Id: Icebd05a930afc5964bc4677357da5d1b23666066 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
This commit is contained in:
parent
b2707a6968
commit
0651b5b77a
|
@ -8,6 +8,7 @@
|
||||||
#define STM32MP_SHARED_RESOURCES_H
|
#define STM32MP_SHARED_RESOURCES_H
|
||||||
|
|
||||||
#include <stdbool.h>
|
#include <stdbool.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
#ifdef STM32MP_SHARED_RESOURCES
|
#ifdef STM32MP_SHARED_RESOURCES
|
||||||
enum stm32mp_shres;
|
enum stm32mp_shres;
|
||||||
|
@ -24,7 +25,20 @@ void stm32mp_register_secure_periph(enum stm32mp_shres id);
|
||||||
/* Register a shared resource assigned to the non-secure world */
|
/* Register a shared resource assigned to the non-secure world */
|
||||||
void stm32mp_register_non_secure_periph(enum stm32mp_shres id);
|
void stm32mp_register_non_secure_periph(enum stm32mp_shres id);
|
||||||
|
|
||||||
|
/* Register a peripheral as secure or non-secure based on IO base address */
|
||||||
|
void stm32mp_register_secure_periph_iomem(uintptr_t base);
|
||||||
|
void stm32mp_register_non_secure_periph_iomem(uintptr_t base);
|
||||||
|
|
||||||
/* Consolidate peripheral states and lock against new peripheral registering */
|
/* Consolidate peripheral states and lock against new peripheral registering */
|
||||||
void stm32mp_lock_periph_registering(void);
|
void stm32mp_lock_periph_registering(void);
|
||||||
|
#else
|
||||||
|
static inline void stm32mp_register_secure_periph_iomem(uintptr_t base __unused)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline
|
||||||
|
void stm32mp_register_non_secure_periph_iomem(uintptr_t base __unused)
|
||||||
|
{
|
||||||
|
}
|
||||||
#endif /* STM32MP_SHARED_RESOURCES */
|
#endif /* STM32MP_SHARED_RESOURCES */
|
||||||
#endif /* STM32MP_SHARED_RESOURCES_H */
|
#endif /* STM32MP_SHARED_RESOURCES_H */
|
||||||
|
|
|
@ -494,14 +494,16 @@ static inline uint32_t tamp_bkpr(uint32_t idx)
|
||||||
#define IWDG2_BASE U(0x5A002000)
|
#define IWDG2_BASE U(0x5A002000)
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* STM32MP1 I2C4
|
* Miscellaneous STM32MP1 peripherals base address
|
||||||
******************************************************************************/
|
|
||||||
#define I2C4_BASE U(0x5C002000)
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* STM32MP1 DBGMCU
|
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
|
#define CRYP1_BASE U(0x54001000)
|
||||||
#define DBGMCU_BASE U(0x50081000)
|
#define DBGMCU_BASE U(0x50081000)
|
||||||
|
#define HASH1_BASE U(0x54002000)
|
||||||
|
#define I2C4_BASE U(0x5C002000)
|
||||||
|
#define I2C6_BASE U(0x5c009000)
|
||||||
|
#define RNG1_BASE U(0x54003000)
|
||||||
|
#define RTC_BASE U(0x5c004000)
|
||||||
|
#define SPI6_BASE U(0x5c001000)
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* Device Tree defines
|
* Device Tree defines
|
||||||
|
|
|
@ -233,6 +233,84 @@ void stm32mp_register_non_secure_periph(enum stm32mp_shres id)
|
||||||
register_periph(id, SHRES_NON_SECURE);
|
register_periph(id, SHRES_NON_SECURE);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void register_periph_iomem(uintptr_t base, unsigned int state)
|
||||||
|
{
|
||||||
|
enum stm32mp_shres id;
|
||||||
|
|
||||||
|
switch (base) {
|
||||||
|
case CRYP1_BASE:
|
||||||
|
id = STM32MP1_SHRES_CRYP1;
|
||||||
|
break;
|
||||||
|
case HASH1_BASE:
|
||||||
|
id = STM32MP1_SHRES_HASH1;
|
||||||
|
break;
|
||||||
|
case I2C4_BASE:
|
||||||
|
id = STM32MP1_SHRES_I2C4;
|
||||||
|
break;
|
||||||
|
case I2C6_BASE:
|
||||||
|
id = STM32MP1_SHRES_I2C6;
|
||||||
|
break;
|
||||||
|
case IWDG1_BASE:
|
||||||
|
id = STM32MP1_SHRES_IWDG1;
|
||||||
|
break;
|
||||||
|
case RNG1_BASE:
|
||||||
|
id = STM32MP1_SHRES_RNG1;
|
||||||
|
break;
|
||||||
|
case RTC_BASE:
|
||||||
|
id = STM32MP1_SHRES_RTC;
|
||||||
|
break;
|
||||||
|
case SPI6_BASE:
|
||||||
|
id = STM32MP1_SHRES_SPI6;
|
||||||
|
break;
|
||||||
|
case USART1_BASE:
|
||||||
|
id = STM32MP1_SHRES_USART1;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case GPIOA_BASE:
|
||||||
|
case GPIOB_BASE:
|
||||||
|
case GPIOC_BASE:
|
||||||
|
case GPIOD_BASE:
|
||||||
|
case GPIOE_BASE:
|
||||||
|
case GPIOF_BASE:
|
||||||
|
case GPIOG_BASE:
|
||||||
|
case GPIOH_BASE:
|
||||||
|
case GPIOI_BASE:
|
||||||
|
case GPIOJ_BASE:
|
||||||
|
case GPIOK_BASE:
|
||||||
|
case USART2_BASE:
|
||||||
|
case USART3_BASE:
|
||||||
|
case UART4_BASE:
|
||||||
|
case UART5_BASE:
|
||||||
|
case USART6_BASE:
|
||||||
|
case UART7_BASE:
|
||||||
|
case UART8_BASE:
|
||||||
|
case IWDG2_BASE:
|
||||||
|
/* Allow drivers to register some non-secure resources */
|
||||||
|
VERBOSE("IO for non-secure resource 0x%x\n",
|
||||||
|
(unsigned int)base);
|
||||||
|
if (state != SHRES_NON_SECURE) {
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
return;
|
||||||
|
|
||||||
|
default:
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
register_periph(id, state);
|
||||||
|
}
|
||||||
|
|
||||||
|
void stm32mp_register_secure_periph_iomem(uintptr_t base)
|
||||||
|
{
|
||||||
|
register_periph_iomem(base, SHRES_SECURE);
|
||||||
|
}
|
||||||
|
|
||||||
|
void stm32mp_register_non_secure_periph_iomem(uintptr_t base)
|
||||||
|
{
|
||||||
|
register_periph_iomem(base, SHRES_NON_SECURE);
|
||||||
|
}
|
||||||
|
|
||||||
static bool stm32mp_gpio_bank_is_non_secure(unsigned int bank)
|
static bool stm32mp_gpio_bank_is_non_secure(unsigned int bank)
|
||||||
{
|
{
|
||||||
unsigned int non_secure = 0U;
|
unsigned int non_secure = 0U;
|
||||||
|
|
Loading…
Reference in New Issue