Changes to support execution in AArch32 state for JUNO
Following steps are required to boot JUNO in AArch32 state: 1> BL1, in AArch64 state, loads BL2. 2> BL2, in AArch64 state, initializes DDR. Loads SP_MIN & BL33 (AArch32 executable)images. Calls RUN_IMAGE SMC to go back to BL1. 3> BL1 writes AArch32 executable opcodes, to load and branch at the entrypoint address of SP_MIN, at HI-VECTOR address and then request for warm reset in AArch32 state using RMR_EL3. This patch makes following changes to facilitate above steps: * Added assembly function to carry out step 3 above. * Added region in TZC that enables Secure access to the HI-VECTOR(0xFFFF0000) address space. * AArch32 image descriptor is used, in BL2, to load SP_MIN and BL33 AArch32 executable images. A new flag `JUNO_AARCH32_EL3_RUNTIME` is introduced that controls above changes. By default this flag is disabled. NOTE: BL1 and BL2 are not supported in AArch32 state for JUNO. Change-Id: I091d56a0e6d36663e6d9d2bb53c92c672195d1ec Signed-off-by: Yatharth Kochar <yatharth.kochar@arm.com> Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
This commit is contained in:
parent
dc787588a5
commit
07570d592e
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@ -261,6 +261,16 @@
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#define DISABLE_ALL_EXCEPTIONS \
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#define DISABLE_ALL_EXCEPTIONS \
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(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
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(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
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/*
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* RMR_EL3 definitions
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*/
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#define RMR_EL3_RR_BIT (1 << 1)
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#define RMR_EL3_AA64_BIT (1 << 0)
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/*
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* HI-VECTOR address for AArch32 state
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*/
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#define HI_VECTOR_BASE (0xFFFF0000)
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/*
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/*
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* TCR defintions
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* TCR defintions
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@ -157,6 +157,7 @@ void arm_bl2_platform_setup(void);
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void arm_bl2_plat_arch_setup(void);
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void arm_bl2_plat_arch_setup(void);
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uint32_t arm_get_spsr_for_bl32_entry(void);
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uint32_t arm_get_spsr_for_bl32_entry(void);
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uint32_t arm_get_spsr_for_bl33_entry(void);
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uint32_t arm_get_spsr_for_bl33_entry(void);
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int arm_bl2_handle_post_image_load(unsigned int image_id);
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/* BL2U utility functions */
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/* BL2U utility functions */
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void arm_bl2u_early_platform_setup(struct meminfo *mem_layout,
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void arm_bl2u_early_platform_setup(struct meminfo *mem_layout,
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@ -96,9 +96,16 @@
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/*
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/*
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* Required platform porting definitions common to all ARM CSS SoCs
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* Required platform porting definitions common to all ARM CSS SoCs
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*/
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*/
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#if JUNO_AARCH32_EL3_RUNTIME
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/*
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* Following change is required to initialize TZC
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* for enabling access to the HI_VECTOR (0xFFFF0000)
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* location needed for JUNO AARCH32 support.
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*/
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#define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x8000)
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#else
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/* 2MB used for SCP DDR retraining */
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/* 2MB used for SCP DDR retraining */
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#define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x00200000)
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#define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x00200000)
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#endif
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#endif /* __SOC_CSS_DEF_H__ */
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#endif /* __SOC_CSS_DEF_H__ */
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@ -34,12 +34,18 @@
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#include <cortex_a53.h>
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#include <cortex_a53.h>
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#include <cortex_a57.h>
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#include <cortex_a57.h>
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#include <cortex_a72.h>
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#include <cortex_a72.h>
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#include <cpu_macros.S>
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#include <css_def.h>
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#include <v2m_def.h>
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#include <v2m_def.h>
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#include "../juno_def.h"
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#include "../juno_def.h"
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.globl plat_reset_handler
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.globl plat_reset_handler
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.globl plat_arm_calc_core_pos
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.globl plat_arm_calc_core_pos
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#if JUNO_AARCH32_EL3_RUNTIME
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.globl plat_get_my_entrypoint
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.globl juno_reset_to_aarch32_state
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#endif
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#define JUNO_REVISION(rev) REV_JUNO_R##rev
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#define JUNO_REVISION(rev) REV_JUNO_R##rev
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#define JUNO_HANDLER(rev) plat_reset_handler_juno_r##rev
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#define JUNO_HANDLER(rev) plat_reset_handler_juno_r##rev
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@ -205,6 +211,20 @@ func plat_reset_handler
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endfunc plat_reset_handler
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endfunc plat_reset_handler
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/* -----------------------------------------------------
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* void juno_do_reset_to_aarch32_state(void);
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*
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* Request warm reset to AArch32 mode.
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* -----------------------------------------------------
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*/
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func juno_do_reset_to_aarch32_state
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mov x0, #RMR_EL3_RR_BIT
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dsb sy
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msr rmr_el3, x0
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isb
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wfi
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endfunc juno_do_reset_to_aarch32_state
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/* -----------------------------------------------------
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/* -----------------------------------------------------
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* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
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* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
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* Helper function to calculate the core position.
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* Helper function to calculate the core position.
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@ -213,3 +233,77 @@ endfunc plat_reset_handler
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func plat_arm_calc_core_pos
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func plat_arm_calc_core_pos
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b css_calc_core_pos_swap_cluster
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b css_calc_core_pos_swap_cluster
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endfunc plat_arm_calc_core_pos
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endfunc plat_arm_calc_core_pos
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#if JUNO_AARCH32_EL3_RUNTIME
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/* ---------------------------------------------------------------------
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* uintptr_t plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between a cold and a warm
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* boot. On JUNO platform, this distinction is based on the contents of
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* the Trusted Mailbox. It is initialised to zero by the SCP before the
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* AP cores are released from reset. Therefore, a zero mailbox means
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* it's a cold reset. If it is a warm boot then a request to reset to
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* AArch32 state is issued. This is the only way to reset to AArch32
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* in EL3 on Juno. A trampoline located at the high vector address
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* has already been prepared by BL1.
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*
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* This functions returns the contents of the mailbox, i.e.:
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* - 0 for a cold boot;
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* - request warm reset in AArch32 state for warm boot case;
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* ---------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
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ldr x0, [x0]
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cbz x0, return
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b juno_do_reset_to_aarch32_state
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1:
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b 1b
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return:
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ret
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endfunc plat_get_my_entrypoint
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/*
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* Emit a "movw r0, #imm16" which moves the lower
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* 16 bits of `_val` into r0.
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*/
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.macro emit_movw _reg_d, _val
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mov_imm \_reg_d, (0xe3000000 | \
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((\_val & 0xfff) | \
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((\_val & 0xf000) << 4)))
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.endm
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/*
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* Emit a "movt r0, #imm16" which moves the upper
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* 16 bits of `_val` into r0.
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*/
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.macro emit_movt _reg_d, _val
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mov_imm \_reg_d, (0xe3400000 | \
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(((\_val & 0x0fff0000) >> 16) | \
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((\_val & 0xf0000000) >> 12)))
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.endm
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/*
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* This function writes the trampoline code at HI-VEC (0xFFFF0000)
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* address which loads r0 with the entrypoint address for
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* BL32 (a.k.a SP_MIN) when EL3 is in AArch32 mode. A warm reset
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* to AArch32 mode is then requested by writing into RMR_EL3.
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*/
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func juno_reset_to_aarch32_state
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emit_movw w0, BL32_BASE
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emit_movt w1, BL32_BASE
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/* opcode "bx r0" to branch using r0 in AArch32 mode */
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mov_imm w2, 0xe12fff10
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/* Write the above opcodes at HI-VECTOR location */
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mov_imm x3, HI_VECTOR_BASE
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str w0, [x3], #4
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str w1, [x3], #4
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str w2, [x3]
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bl juno_do_reset_to_aarch32_state
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1:
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b 1b
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endfunc juno_reset_to_aarch32_state
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#endif /* JUNO_AARCH32_EL3_RUNTIME */
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* modification, are permitted provided that the following conditions are met:
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@ -32,11 +32,15 @@
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#include <errno.h>
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#include <errno.h>
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#include <platform.h>
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#include <platform.h>
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#include <plat_arm.h>
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#include <plat_arm.h>
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#include <sp805.h>
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#include <tbbr_img_def.h>
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#include <tbbr_img_def.h>
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#include <v2m_def.h>
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#include <v2m_def.h>
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#define RESET_REASON_WDOG_RESET (0x2)
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#define RESET_REASON_WDOG_RESET (0x2)
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void juno_reset_to_aarch32_state(void);
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/*******************************************************************************
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/*******************************************************************************
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* The following function checks if Firmware update is needed,
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* The following function checks if Firmware update is needed,
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* by checking if TOC in FIP image is valid or watchdog reset happened.
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* by checking if TOC in FIP image is valid or watchdog reset happened.
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@ -85,3 +89,15 @@ __dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved)
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while (1)
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while (1)
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wfi();
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wfi();
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}
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}
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#if JUNO_AARCH32_EL3_RUNTIME
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void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
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{
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#if !ARM_DISABLE_TRUSTED_WDOG
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/* Disable watchdog before leaving BL1 */
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sp805_stop(ARM_SP805_TWDG_BASE);
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#endif
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juno_reset_to_aarch32_state();
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}
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#endif /* JUNO_AARCH32_EL3_RUNTIME */
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@ -0,0 +1,56 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include <bl_common.h>
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#include <desc_image_load.h>
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#include <plat_arm.h>
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#if JUNO_AARCH32_EL3_RUNTIME
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/*******************************************************************************
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* This function changes the spsr for BL32 image to bypass
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* the check in BL1 AArch64 exception handler. This is needed in the aarch32
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* boot flow as the core comes up in aarch64 and to enter the BL32 image a warm
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* reset in aarch32 state is required.
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******************************************************************************/
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int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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int err = arm_bl2_handle_post_image_load(image_id);
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if (!err && (image_id == BL32_IMAGE_ID)) {
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bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
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assert(bl_mem_params);
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bl_mem_params->ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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}
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return err;
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}
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#endif /* JUNO_AARCH32_EL3_RUNTIME */
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@ -48,8 +48,14 @@ endif
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PLAT_INCLUDES := -Iplat/arm/board/juno/include
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PLAT_INCLUDES := -Iplat/arm/board/juno/include
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PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/aarch64/juno_helpers.S
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PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S
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# Flag to enable support for AArch32 state on JUNO
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JUNO_AARCH32_EL3_RUNTIME := 0
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$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME))
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$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME))
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ifeq (${ARCH},aarch64)
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BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \
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BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a57.S \
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lib/cpus/aarch64/cortex_a57.S \
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lib/cpus/aarch64/cortex_a72.S \
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lib/cpus/aarch64/cortex_a72.S \
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@ -59,6 +65,7 @@ BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \
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${JUNO_SECURITY_SOURCES}
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${JUNO_SECURITY_SOURCES}
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BL2_SOURCES += plat/arm/board/juno/juno_err.c \
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BL2_SOURCES += plat/arm/board/juno/juno_err.c \
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plat/arm/board/juno/juno_bl2_setup.c \
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${JUNO_SECURITY_SOURCES}
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${JUNO_SECURITY_SOURCES}
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BL2U_SOURCES += ${JUNO_SECURITY_SOURCES}
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BL2U_SOURCES += ${JUNO_SECURITY_SOURCES}
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@ -71,6 +78,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
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${JUNO_GIC_SOURCES} \
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${JUNO_GIC_SOURCES} \
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${JUNO_INTERCONNECT_SOURCES} \
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${JUNO_INTERCONNECT_SOURCES} \
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${JUNO_SECURITY_SOURCES}
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${JUNO_SECURITY_SOURCES}
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endif
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# Enable workarounds for selected Cortex-A53 and A57 errata.
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# Enable workarounds for selected Cortex-A53 and A57 errata.
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ERRATA_A53_855873 := 1
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ERRATA_A53_855873 := 1
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@ -44,6 +44,7 @@
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#pragma weak bl1_plat_arch_setup
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#pragma weak bl1_plat_arch_setup
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#pragma weak bl1_platform_setup
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#pragma weak bl1_platform_setup
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#pragma weak bl1_plat_sec_mem_layout
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#pragma weak bl1_plat_sec_mem_layout
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#pragma weak bl1_plat_prepare_exit
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/* Data structure which holds the extents of the trusted SRAM for BL1*/
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/* Data structure which holds the extents of the trusted SRAM for BL1*/
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@ -249,11 +249,7 @@ void bl2_plat_arch_setup(void)
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}
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}
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#if LOAD_IMAGE_V2
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#if LOAD_IMAGE_V2
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||||||
/*******************************************************************************
|
int arm_bl2_handle_post_image_load(unsigned int image_id)
|
||||||
* This function can be used by the platforms to update/use image
|
|
||||||
* information for given `image_id`.
|
|
||||||
******************************************************************************/
|
|
||||||
int bl2_plat_handle_post_image_load(unsigned int image_id)
|
|
||||||
{
|
{
|
||||||
int err = 0;
|
int err = 0;
|
||||||
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
|
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
|
||||||
|
@ -286,6 +282,15 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function can be used by the platforms to update/use image
|
||||||
|
* information for given `image_id`.
|
||||||
|
******************************************************************************/
|
||||||
|
int bl2_plat_handle_post_image_load(unsigned int image_id)
|
||||||
|
{
|
||||||
|
return arm_bl2_handle_post_image_load(image_id);
|
||||||
|
}
|
||||||
|
|
||||||
#else /* LOAD_IMAGE_V2 */
|
#else /* LOAD_IMAGE_V2 */
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
|
|
|
@ -137,8 +137,14 @@ BL2_SOURCES += drivers/io/io_fip.c \
|
||||||
plat/arm/common/arm_bl2_setup.c \
|
plat/arm/common/arm_bl2_setup.c \
|
||||||
plat/arm/common/arm_io_storage.c
|
plat/arm/common/arm_io_storage.c
|
||||||
ifeq (${LOAD_IMAGE_V2},1)
|
ifeq (${LOAD_IMAGE_V2},1)
|
||||||
BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c\
|
# Because BL1/BL2 execute in AArch64 mode but BL32 in AArch32 we need to use
|
||||||
plat/arm/common/arm_image_load.c \
|
# the AArch32 descriptors.
|
||||||
|
ifeq (${JUNO_AARCH32_EL3_RUNTIME},1)
|
||||||
|
BL2_SOURCES += plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
|
||||||
|
else
|
||||||
|
BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c
|
||||||
|
endif
|
||||||
|
BL2_SOURCES += plat/arm/common/arm_image_load.c \
|
||||||
common/desc_image_load.c
|
common/desc_image_load.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue