Merge pull request #1833 from marex/arm/master/pci-v2.0.0
rcar_gen3: plat: Prevent PCIe hang during L1X config access
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commit
085c39cf2e
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@ -13,6 +13,9 @@ GENERATE_COT := 1
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BL2_AT_EL3 := 1
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BL2_AT_EL3 := 1
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ENABLE_SVE_FOR_NS := 0
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ENABLE_SVE_FOR_NS := 0
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CRASH_REPORTING := 1
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HANDLE_EA_EL3_FIRST := 1
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$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
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$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
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ifeq (${SPD},none)
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ifeq (${SPD},none)
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@ -322,8 +325,8 @@ PLAT_INCLUDES := -Idrivers/staging/renesas/rcar/ddr \
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-Iplat/renesas/rcar/include \
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-Iplat/renesas/rcar/include \
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-Iplat/renesas/rcar
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-Iplat/renesas/rcar
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PLAT_BL_COMMON_SOURCES := drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
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PLAT_BL_COMMON_SOURCES := drivers/renesas/rcar/iic_dvfs/iic_dvfs.c \
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plat/renesas/rcar/rcar_common.c
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RCAR_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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RCAR_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v2/gicv2_main.c \
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drivers/arm/gic/v2/gicv2_main.c \
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@ -0,0 +1,69 @@
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/*
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* Copyright (c) 2019, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <drivers/console.h>
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#include <lib/xlat_tables/xlat_mmu_helpers.h>
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#include <plat/common/platform.h>
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#include <lib/mmio.h>
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#define CPG_BASE 0xE6150000
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#define CPG_MSTPSR3 0x0048
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#define MSTP318 (1 << 18)
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#define MSTP319 (1 << 19)
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#define PMSR 0x5c
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#define PMSR_L1FAEG (1 << 31)
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#define PMSR_PMEL1RX (1 << 23)
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#define PMCTLR 0x60
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#define PMSR_L1IATN (1 << 31)
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static int rcar_pcie_fixup(unsigned int controller)
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{
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uint32_t rcar_pcie_base[] = { 0xfe011000, 0xee811000 };
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uint32_t addr = rcar_pcie_base[controller];
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uint32_t cpg, pmsr;
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int ret = 0;
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/* Test if PCIECx is enabled */
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cpg = mmio_read_32(CPG_BASE + CPG_MSTPSR3);
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if (cpg & (MSTP318 << !controller))
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return ret;
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pmsr = mmio_read_32(addr + PMSR);
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if ((pmsr & PMSR_PMEL1RX) && ((pmsr & 0x70000) != 0x30000)) {
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/* Fix applicable */
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mmio_write_32(addr + PMCTLR, PMSR_L1IATN);
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while (!(mmio_read_32(addr + PMSR) & PMSR_L1FAEG))
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;
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mmio_write_32(addr + PMSR, PMSR_L1FAEG | PMSR_PMEL1RX);
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ret = 1;
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}
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return ret;
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}
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/* RAS functions common to AArch64 ARM platforms */
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void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
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void *handle, uint64_t flags)
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{
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unsigned int fixed = 0;
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fixed |= rcar_pcie_fixup(0);
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fixed |= rcar_pcie_fixup(1);
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if (fixed)
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return;
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ERROR("Unhandled External Abort received on 0x%lx at EL3!\n",
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read_mpidr_el1());
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ERROR(" exception reason=%u syndrome=0x%llx\n", ea_reason, syndrome);
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panic();
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}
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