From 08695df91dffb2e45c01866b760d73cb531a071b Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Tue, 20 Jul 2021 17:14:32 +0800 Subject: [PATCH] refactor(plat/nxp): refine api to read SVR register 1. Refined struct soc_info_t definition. 2. Refined get_soc_info function. 3. Fixed some SVR persernality value. 4. Refined API to get cluster numbers and cores per cluster. Signed-off-by: Jiafei Pan Change-Id: I3c20611a523516cc63330dce4c925e6cda1e93c4 --- drivers/nxp/dcfg/dcfg.c | 14 ++------ drivers/nxp/ddr/phy-gen2/phy.c | 14 ++++---- include/drivers/nxp/dcfg/dcfg.h | 36 +++++++++++++++------ include/drivers/nxp/dcfg/dcfg_lsch2.h | 8 ++--- plat/nxp/common/setup/include/plat_common.h | 15 +++++---- plat/nxp/common/setup/ls_common.c | 26 ++++++++++++++- plat/nxp/soc-lx2160a/include/soc.h | 11 +++---- plat/nxp/soc-lx2160a/soc.c | 35 ++++++-------------- 8 files changed, 88 insertions(+), 71 deletions(-) diff --git a/drivers/nxp/dcfg/dcfg.c b/drivers/nxp/dcfg/dcfg.c index 2e813e780..a988c5dd0 100644 --- a/drivers/nxp/dcfg/dcfg.c +++ b/drivers/nxp/dcfg/dcfg.c @@ -1,5 +1,5 @@ /* - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * * SPDX-License-Identifier: BSD-3-Clause * @@ -43,20 +43,12 @@ const soc_info_t *get_soc_info(void) reg = gur_in32(dcfg_init_info->g_nxp_dcfg_addr + DCFG_SVR_OFFSET); - soc_info.mfr_id = (reg & SVR_MFR_ID_MASK) >> SVR_MFR_ID_SHIFT; -#if defined(CONFIG_CHASSIS_3_2) - soc_info.family = (reg & SVR_FAMILY_MASK) >> SVR_FAMILY_SHIFT; - soc_info.dev_id = (reg & SVR_DEV_ID_MASK) >> SVR_DEV_ID_SHIFT; -#endif + soc_info.svr_reg.val = reg; + /* zero means SEC enabled. */ soc_info.sec_enabled = (((reg & SVR_SEC_MASK) >> SVR_SEC_SHIFT) == 0) ? true : false; - soc_info.personality = (reg & SVR_PERSONALITY_MASK) - >> SVR_PERSONALITY_SHIFT; - soc_info.maj_ver = (reg & SVR_MAJ_VER_MASK) >> SVR_MAJ_VER_SHIFT; - soc_info.min_ver = reg & SVR_MIN_VER_MASK; - soc_info.is_populated = true; return (const soc_info_t *) &soc_info; } diff --git a/drivers/nxp/ddr/phy-gen2/phy.c b/drivers/nxp/ddr/phy-gen2/phy.c index 97de1ae99..9c84b00f7 100644 --- a/drivers/nxp/ddr/phy-gen2/phy.c +++ b/drivers/nxp/ddr/phy-gen2/phy.c @@ -672,7 +672,7 @@ static void prog_seq0bdly0(uint16_t *phy, #ifdef DDR_PLL_FIX soc_info = get_soc_info(); - if (soc_info->maj_ver == 1) { + if (soc_info->svr_reg.bf.maj_ver == 1) { ps_count[0] = 0x520; /* seq0bdly0 */ ps_count[1] = 0xa41; /* seq0bdly1 */ ps_count[2] = 0x668a; /* seq0bdly2 */ @@ -1093,8 +1093,8 @@ static void prog_dfi_rd_data_cs_dest_map(uint16_t *phy, #ifdef ERRATA_DDR_A011396 /* Only apply to DDRC 5.05.00 */ - soc_info = get_soc_info(NXP_DCFG_ADDR); - if ((soc_info->maj_ver == 1U) && (ip_rev == U(0x50500))) { + soc_info = get_soc_info(); + if ((soc_info->svr_reg.bf.maj_ver == 1U) && (ip_rev == U(0x50500))) { phy_io_write16(phy, t_master | csr_dfi_rd_data_cs_dest_map_addr, 0U); @@ -1890,8 +1890,8 @@ static int c_init_phy_config(uint16_t **phy_ptr, prog_pll_ctrl2(phy, input); #ifdef DDR_PLL_FIX soc_info = get_soc_info(); - debug("SOC_SI_REV = %x\n", soc_info->maj_ver); - if (soc_info->maj_ver == 1) { + debug("SOC_SI_REV = %x\n", soc_info->svr_reg.bf.maj_ver); + if (soc_info->svr_reg.bf.maj_ver == 1) { prog_pll_pwr_dn(phy, input); /*Enable FFE aka TxEqualizationMode for rev1 SI*/ @@ -2601,8 +2601,8 @@ int compute_ddr_phy(struct ddr_info *priv) } #ifdef NXP_APPLY_MAX_CDD - soc_info = get_soc_info(NXP_DCFG_ADDR); - if (soc_info->maj_ver == 2) { + soc_info = get_soc_info(); + if (soc_info->svr_reg.bf.maj_ver == 2) { tcfg0 = regs->timing_cfg[0]; tcfg4 = regs->timing_cfg[4]; rank = findrank(conf->cs_in_use); diff --git a/include/drivers/nxp/dcfg/dcfg.h b/include/drivers/nxp/dcfg/dcfg.h index 3f4855ae5..524450a82 100644 --- a/include/drivers/nxp/dcfg/dcfg.h +++ b/include/drivers/nxp/dcfg/dcfg.h @@ -27,23 +27,41 @@ #endif typedef struct { - bool is_populated; - uint8_t mfr_id; -#if defined(CONFIG_CHASSIS_3_2) - uint8_t family; - uint8_t dev_id; + union { + uint32_t val; + struct { + uint32_t min_ver:4; + uint32_t maj_ver:4; +#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) + uint32_t personality:6; + uint32_t rsv1:2; +#elif defined(CONFIG_CHASSIS_2) + uint32_t personality:8; + #endif - uint8_t personality; +#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) + uint32_t dev_id:6; + uint32_t rsv2:2; + uint32_t family:4; +#elif defined(CONFIG_CHASSIS_2) + uint32_t dev_id:12; +#endif + uint32_t mfr_id; + } __packed bf; + struct { + uint32_t maj_min:8; + uint32_t version; /* SoC version without major and minor info */ + } __packed bf_ver; + } __packed svr_reg; bool sec_enabled; - uint8_t maj_ver; - uint8_t min_ver; + bool is_populated; } soc_info_t; typedef struct { bool is_populated; uint8_t ocram_present; uint8_t ddrc1_present; -#if defined(CONFIG_CHASSIS_3_2) +#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) uint8_t ddrc2_present; #endif } devdisr5_info_t; diff --git a/include/drivers/nxp/dcfg/dcfg_lsch2.h b/include/drivers/nxp/dcfg/dcfg_lsch2.h index 2838aca98..1e5672910 100644 --- a/include/drivers/nxp/dcfg/dcfg_lsch2.h +++ b/include/drivers/nxp/dcfg/dcfg_lsch2.h @@ -34,12 +34,10 @@ #define SVR_MFR_ID_MASK 0xF0000000 #define SVR_MFR_ID_SHIFT 28 -#define SVR_FAMILY_MASK 0xF000000 -#define SVR_FAMILY_SHIFT 24 -#define SVR_DEV_ID_MASK 0x3F0000 +#define SVR_DEV_ID_MASK 0xFFF0000 #define SVR_DEV_ID_SHIFT 16 -#define SVR_PERSONALITY_MASK 0x3E00 -#define SVR_PERSONALITY_SHIFT 9 +#define SVR_PERSONALITY_MASK 0xFF00 +#define SVR_PERSONALITY_SHIFT 8 #define SVR_SEC_MASK 0x100 #define SVR_SEC_SHIFT 8 #define SVR_MAJ_VER_MASK 0xF0 diff --git a/plat/nxp/common/setup/include/plat_common.h b/plat/nxp/common/setup/include/plat_common.h index 18d36ca26..97a9cb7f5 100644 --- a/plat/nxp/common/setup/include/plat_common.h +++ b/plat/nxp/common/setup/include/plat_common.h @@ -1,5 +1,5 @@ /* - * Copyright 2018-2020 NXP + * Copyright 2018-2021 NXP * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,7 +10,9 @@ #include +#include #include + #include #ifdef IMAGE_BL31 @@ -129,18 +131,19 @@ void ls_setup_page_tables(uintptr_t total_base, #endif ); - /* Structure to define SoC personality */ struct soc_type { char name[10]; - uint32_t personality; - uint32_t num_clusters; - uint32_t cores_per_cluster; + uint32_t version; + uint8_t num_clusters; + uint8_t cores_per_cluster; }; +void get_cluster_info(const struct soc_type *soc_list, uint8_t ps_count, + uint8_t *num_clusters, uint8_t *cores_per_cluster); #define SOC_ENTRY(n, v, ncl, nc) { \ .name = #n, \ - .personality = SVR_##v, \ + .version = SVR_##v, \ .num_clusters = (ncl), \ .cores_per_cluster = (nc)} diff --git a/plat/nxp/common/setup/ls_common.c b/plat/nxp/common/setup/ls_common.c index a6946e1a8..e7ae06082 100644 --- a/plat/nxp/common/setup/ls_common.c +++ b/plat/nxp/common/setup/ls_common.c @@ -1,5 +1,5 @@ /* - * Copyright 2018-2020 NXP + * Copyright 2018-2021 NXP * * SPDX-License-Identifier: BSD-3-Clause * @@ -238,3 +238,27 @@ const mmap_region_t *plat_ls_get_mmap(void) { return plat_ls_mmap; } + +/* + * This function get the number of clusters and cores count per cluster + * in the SoC. + */ +void get_cluster_info(const struct soc_type *soc_list, uint8_t ps_count, + uint8_t *num_clusters, uint8_t *cores_per_cluster) +{ + const soc_info_t *soc_info = get_soc_info(); + *num_clusters = NUMBER_OF_CLUSTERS; + *cores_per_cluster = CORES_PER_CLUSTER; + unsigned int i; + + for (i = 0U; i < ps_count; i++) { + if (soc_list[i].version == soc_info->svr_reg.bf_ver.version) { + *num_clusters = soc_list[i].num_clusters; + *cores_per_cluster = soc_list[i].cores_per_cluster; + break; + } + } + + VERBOSE("NUM of cluster = 0x%x, Cores per cluster = 0x%x\n", + *num_clusters, *cores_per_cluster); +} diff --git a/plat/nxp/soc-lx2160a/include/soc.h b/plat/nxp/soc-lx2160a/include/soc.h index bd236201c..7cc4a03eb 100644 --- a/plat/nxp/soc-lx2160a/include/soc.h +++ b/plat/nxp/soc-lx2160a/include/soc.h @@ -1,5 +1,5 @@ /* - * Copyright 2018-2020 NXP + * Copyright 2018-2021 NXP * * SPDX-License-Identifier: BSD-3-Clause * @@ -52,11 +52,10 @@ #define FLEXSPI_NOR 0xf /* End: Macros used by soc.c: get_boot_dev */ -/* bits */ -/* SVR Definition */ -#define SVR_LX2160A 0x04 -#define SVR_LX2120A 0x14 -#define SVR_LX2080A 0x05 +/* SVR Definition (not include major and minor rev) */ +#define SVR_LX2160A 0x873601 +#define SVR_LX2120A 0x873621 +#define SVR_LX2080A 0x873603 /* Number of cores in platform */ /* Used by common code for array initialization */ diff --git a/plat/nxp/soc-lx2160a/soc.c b/plat/nxp/soc-lx2160a/soc.c index 5c77540a7..2209fdad8 100644 --- a/plat/nxp/soc-lx2160a/soc.c +++ b/plat/nxp/soc-lx2160a/soc.c @@ -82,28 +82,6 @@ static const ccn_desc_t plat_ccn_desc = { .master_to_rn_id_map = master_to_rn_id_map }; -/******************************************************************************* - * This function returns the number of clusters in the SoC - ******************************************************************************/ -static unsigned int get_num_cluster(void) -{ - const soc_info_t *soc_info = get_soc_info(); - uint32_t num_clusters = NUMBER_OF_CLUSTERS; - unsigned int i; - - for (i = 0U; i < ARRAY_SIZE(soc_list); i++) { - if (soc_list[i].personality == soc_info->personality) { - num_clusters = soc_list[i].num_clusters; - break; - } - } - - VERBOSE("NUM of cluster = 0x%x\n", num_clusters); - - return num_clusters; -} - - /****************************************************************************** * Function returns the base counter frequency * after reading the first entry at CNTFID0 (0x20 offset). @@ -142,8 +120,10 @@ static gpio_init_info_t gpio_init_data = { static void soc_interconnect_config(void) { unsigned long long val = 0x0U; + uint8_t num_clusters, cores_per_cluster; - uint32_t num_clusters = get_num_cluster(); + get_cluster_info(soc_list, ARRAY_SIZE(soc_list), + &num_clusters, &cores_per_cluster); if (num_clusters == 6U) { ccn_init(&plat_six_cluster_ccn_desc); @@ -464,7 +444,12 @@ void soc_platform_setup(void) ******************************************************************************/ void soc_init(void) { - /* low-level init of the soc */ + uint8_t num_clusters, cores_per_cluster; + + get_cluster_info(soc_list, ARRAY_SIZE(soc_list), + &num_clusters, &cores_per_cluster); + + /* low-level init of the soc */ soc_init_start(); soc_init_percpu(); _init_global_data(); @@ -476,8 +461,6 @@ void soc_init(void) panic(); } - uint32_t num_clusters = get_num_cluster(); - if (num_clusters == 6U) { ccn_init(&plat_six_cluster_ccn_desc); } else {