Merge pull request #1176 from wjliang/zynqmp-ipi-mb-svc
plat: xilinx: Add ZynqMP IPI mailbox service [v4]
This commit is contained in:
davidcunado-arm
GitHub
commit
08e06be819
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@ -0,0 +1,129 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* Top-level SMC handler for ZynqMP IPI Mailbox doorbell functions.
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*/
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#include <bakery_lock.h>
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#include <debug.h>
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#include <errno.h>
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#include <mmio.h>
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#include <runtime_svc.h>
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#include <string.h>
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#include "ipi_mailbox_svc.h"
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#include "../zynqmp_ipi.h"
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#include "../zynqmp_private.h"
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#include "../../../services/spd/trusty/smcall.h"
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/*********************************************************************
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* Macros definitions
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********************************************************************/
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/* IPI SMC calls macros: */
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#define IPI_SMC_OPEN_IRQ_MASK 0x00000001U /* IRQ enable bit in IPI
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* open SMC call
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*/
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#define IPI_SMC_NOTIFY_BLOCK_MASK 0x00000001U /* Flag to indicate if
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* IPI notification needs
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* to be blocking.
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*/
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#define IPI_SMC_ENQUIRY_DIRQ_MASK 0x00000001U /* Flag to indicate if
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* notification interrupt
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* to be disabled.
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*/
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#define IPI_SMC_ACK_EIRQ_MASK 0x00000001U /* Flag to indicate if
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* notification interrupt
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* to be enable.
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*/
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#define UNSIGNED32_MASK 0xFFFFFFFFU /* 32bit mask */
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/**
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* ipi_smc_handler() - SMC handler for IPI SMC calls
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*
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* @smc_fid - Function identifier
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* @x1 - x4 - Arguments
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* @cookie - Unused
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* @handler - Pointer to caller's context structure
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*
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* @return - Unused
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*
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* Determines that smc_fid is valid and supported PM SMC Function ID from the
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* list of pm_api_ids, otherwise completes the request with
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* the unknown SMC Function ID
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*
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* The SMC calls for PM service are forwarded from SIP Service SMC handler
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* function with rt_svc_handle signature
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*/
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uint64_t ipi_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
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uint64_t x3, uint64_t x4, void *cookie,
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void *handle, uint64_t flags)
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{
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int ret;
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uint32_t ipi_local_id;
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uint32_t ipi_remote_id;
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unsigned int is_secure;
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ipi_local_id = x1 & UNSIGNED32_MASK;
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ipi_remote_id = x2 & UNSIGNED32_MASK;
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if (SMC_ENTITY(smc_fid) >= SMC_ENTITY_TRUSTED_APP)
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is_secure = 1;
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else
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is_secure = 0;
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/* Validate IPI mailbox access */
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ret = ipi_mb_validate(ipi_local_id, ipi_remote_id, is_secure);
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if (ret)
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SMC_RET1(handle, ret);
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switch (SMC_FUNCTION(smc_fid)) {
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case IPI_MAILBOX_OPEN:
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ipi_mb_open(ipi_local_id, ipi_remote_id);
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SMC_RET1(handle, 0);
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case IPI_MAILBOX_RELEASE:
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ipi_mb_release(ipi_local_id, ipi_remote_id);
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SMC_RET1(handle, 0);
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case IPI_MAILBOX_STATUS_ENQUIRY:
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{
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int disable_irq;
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disable_irq = (x3 & IPI_SMC_ENQUIRY_DIRQ_MASK) ? 1 : 0;
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ret = ipi_mb_enquire_status(ipi_local_id, ipi_remote_id);
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if ((ret & IPI_MB_STATUS_RECV_PENDING) && disable_irq)
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ipi_mb_disable_irq(ipi_local_id, ipi_remote_id);
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SMC_RET1(handle, ret);
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}
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case IPI_MAILBOX_NOTIFY:
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{
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uint32_t is_blocking;
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is_blocking = (x3 & IPI_SMC_NOTIFY_BLOCK_MASK) ? 1 : 0;
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ipi_mb_notify(ipi_local_id, ipi_remote_id, is_blocking);
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SMC_RET1(handle, 0);
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}
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case IPI_MAILBOX_ACK:
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{
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int enable_irq;
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enable_irq = (x3 & IPI_SMC_ACK_EIRQ_MASK) ? 1 : 0;
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ipi_mb_ack(ipi_local_id, ipi_remote_id);
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if (enable_irq)
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ipi_mb_enable_irq(ipi_local_id, ipi_remote_id);
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SMC_RET1(handle, 0);
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}
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case IPI_MAILBOX_ENABLE_IRQ:
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ipi_mb_enable_irq(ipi_local_id, ipi_remote_id);
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SMC_RET1(handle, 0);
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case IPI_MAILBOX_DISABLE_IRQ:
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ipi_mb_disable_irq(ipi_local_id, ipi_remote_id);
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SMC_RET1(handle, 0);
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default:
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WARN("Unimplemented IPI service call: 0x%x\n", smc_fid);
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SMC_RET1(handle, SMC_UNK);
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}
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}
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@ -0,0 +1,39 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* ZynqMP IPI mailbox doorbell service enums and defines */
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#ifndef _IPI_MAILBOX_SVC_H_
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#define _IPI_MAILBOX_SVC_H_
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#include <stdint.h>
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/*********************************************************************
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* Enum definitions
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********************************************************************/
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/* IPI SMC function numbers enum definition */
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enum ipi_api_id {
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/* IPI mailbox operations functions: */
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IPI_MAILBOX_OPEN = 0x1000,
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IPI_MAILBOX_RELEASE,
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IPI_MAILBOX_STATUS_ENQUIRY,
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IPI_MAILBOX_NOTIFY,
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IPI_MAILBOX_ACK,
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IPI_MAILBOX_ENABLE_IRQ,
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IPI_MAILBOX_DISABLE_IRQ
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};
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/*********************************************************************
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* IPI mailbox service APIs declarations
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********************************************************************/
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/* IPI SMC handler */
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uint64_t ipi_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
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uint64_t x3, uint64_t x4, void *cookie, void *handle,
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uint64_t flags);
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#endif /* _IPI_MAILBOX_SVC_H_ */
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@ -42,7 +42,8 @@ $(eval $(call add_define_val,ZYNQMP_CONSOLE,ZYNQMP_CONSOLE_ID_${ZYNQMP_CONSOLE})
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PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
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-Iinclude/plat/arm/common/aarch64/ \
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-Iplat/xilinx/zynqmp/include/ \
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-Iplat/xilinx/zynqmp/pm_service/
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-Iplat/xilinx/zynqmp/pm_service/ \
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-Iplat/xilinx/zynqmp/ipi_mailbox_service/
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PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
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lib/xlat_tables/aarch64/xlat_tables.c \
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@ -71,7 +72,9 @@ BL31_SOURCES += drivers/arm/cci/cci.c \
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plat/xilinx/zynqmp/plat_startup.c \
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plat/xilinx/zynqmp/plat_topology.c \
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plat/xilinx/zynqmp/sip_svc_setup.c \
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plat/xilinx/zynqmp/zynqmp_ipi.c \
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plat/xilinx/zynqmp/pm_service/pm_svc_main.c \
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plat/xilinx/zynqmp/pm_service/pm_api_sys.c \
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plat/xilinx/zynqmp/pm_service/pm_ipi.c \
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plat/xilinx/zynqmp/pm_service/pm_client.c
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plat/xilinx/zynqmp/pm_service/pm_client.c \
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plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.c
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -542,7 +542,6 @@ enum pm_ret_status pm_get_chipid(uint32_t *value)
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*/
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void pm_get_callbackdata(uint32_t *data, size_t count)
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{
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pm_ipi_buff_read_callb(data, count);
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pm_ipi_irq_clear();
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pm_ipi_irq_clear(primary_proc);
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}
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@ -21,13 +21,13 @@
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/**
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* pm_ipi - struct for capturing IPI-channel specific info
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* @mask mask for enabling/disabling and triggering the IPI
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* @base base address for IPI
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* @apu_ipi_id APU IPI agent ID
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* @pmu_ipi_id PMU Agent ID
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* @buffer_base base address for payload buffer
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*/
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struct pm_ipi {
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const unsigned int mask;
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const uintptr_t base;
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const uint32_t apu_ipi_id;
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const uint32_t pmu_ipi_id;
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const uintptr_t buffer_base;
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};
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -8,28 +8,17 @@
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#include <bakery_lock.h>
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#include <mmio.h>
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#include <platform.h>
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#include "../zynqmp_ipi.h"
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#include "../zynqmp_private.h"
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#include "pm_ipi.h"
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/* IPI message buffers */
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#define IPI_BUFFER_BASEADDR 0xFF990000U
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#define IPI_BUFFER_RPU_0_BASE (IPI_BUFFER_BASEADDR + 0x0U)
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#define IPI_BUFFER_RPU_1_BASE (IPI_BUFFER_BASEADDR + 0x200U)
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#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U)
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#define IPI_BUFFER_PL_0_BASE (IPI_BUFFER_BASEADDR + 0x600U)
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#define IPI_BUFFER_PL_1_BASE (IPI_BUFFER_BASEADDR + 0x800U)
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#define IPI_BUFFER_PL_2_BASE (IPI_BUFFER_BASEADDR + 0xA00U)
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#define IPI_BUFFER_PL_3_BASE (IPI_BUFFER_BASEADDR + 0xC00U)
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#define IPI_BUFFER_PMU_BASE (IPI_BUFFER_BASEADDR + 0xE00U)
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#define IPI_BUFFER_TARGET_RPU_0_OFFSET 0x0U
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#define IPI_BUFFER_TARGET_RPU_1_OFFSET 0x40U
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#define IPI_BUFFER_TARGET_APU_OFFSET 0x80U
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#define IPI_BUFFER_TARGET_PL_0_OFFSET 0xC0U
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#define IPI_BUFFER_TARGET_PL_1_OFFSET 0x100U
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#define IPI_BUFFER_TARGET_PL_2_OFFSET 0x140U
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#define IPI_BUFFER_TARGET_PL_3_OFFSET 0x180U
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#define IPI_BUFFER_TARGET_PMU_OFFSET 0x1C0U
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#define IPI_BUFFER_MAX_WORDS 8
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@ -37,75 +26,32 @@
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#define IPI_BUFFER_REQ_OFFSET 0x0U
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#define IPI_BUFFER_RESP_OFFSET 0x20U
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/* IPI Base Address */
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#define IPI_BASEADDR 0XFF300000
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/* APU's IPI registers */
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#define IPI_APU_ISR (IPI_BASEADDR + 0X00000010)
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#define IPI_APU_IER (IPI_BASEADDR + 0X00000018)
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#define IPI_APU_IDR (IPI_BASEADDR + 0X0000001C)
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#define IPI_APU_IXR_PMU_0_MASK (1 << 16)
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#define IPI_TRIG_OFFSET 0
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#define IPI_OBS_OFFSET 4
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/* Power Management IPI interrupt number */
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#define PM_INT_NUM 0
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#define IPI_PMU_PM_INT_BASE (IPI_PMU_0_TRIG + (PM_INT_NUM * 0x1000))
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#define IPI_PMU_PM_INT_MASK (IPI_APU_IXR_PMU_0_MASK << PM_INT_NUM)
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#if (PM_INT_NUM < 0 || PM_INT_NUM > 3)
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#error PM_INT_NUM value out of range
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#endif
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#define IPI_APU_MASK 1U
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DEFINE_BAKERY_LOCK(pm_secure_lock);
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const struct pm_ipi apu_ipi = {
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.mask = IPI_APU_MASK,
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.base = IPI_BASEADDR,
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.apu_ipi_id = IPI_ID_APU,
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.pmu_ipi_id = IPI_ID_PMU0,
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.buffer_base = IPI_BUFFER_APU_BASE,
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};
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/**
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* pm_ipi_init() - Initialize IPI peripheral for communication with PMU
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*
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* @proc Pointer to the processor who is initiating request
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* @return On success, the initialization function must return 0.
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* Any other return value will cause the framework to ignore
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* the service
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*
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* Called from pm_setup initialization function
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*/
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int pm_ipi_init(void)
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int pm_ipi_init(const struct pm_proc *proc)
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{
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bakery_lock_init(&pm_secure_lock);
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/* IPI Interrupts Clear & Disable */
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mmio_write_32(IPI_APU_ISR, 0xffffffff);
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mmio_write_32(IPI_APU_IDR, 0xffffffff);
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ipi_mb_open(proc->ipi->apu_ipi_id, proc->ipi->pmu_ipi_id);
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return 0;
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}
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/**
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* pm_ipi_wait() - wait for pmu to handle request
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* @proc proc which is waiting for PMU to handle request
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*/
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static enum pm_ret_status pm_ipi_wait(const struct pm_proc *proc)
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{
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int status;
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/* Wait until previous interrupt is handled by PMU */
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do {
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status = mmio_read_32(proc->ipi->base + IPI_OBS_OFFSET) &
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IPI_PMU_PM_INT_MASK;
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/* TODO: 1) Use timer to add delay between read attempts */
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/* TODO: 2) Return PM_RET_ERR_TIMEOUT if this times out */
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} while (status);
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return PM_RET_SUCCESS;
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}
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/**
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* pm_ipi_send_common() - Sends IPI request to the PMU
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* @proc Pointer to the processor who is initiating request
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@ -124,16 +70,13 @@ static enum pm_ret_status pm_ipi_send_common(const struct pm_proc *proc,
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IPI_BUFFER_TARGET_PMU_OFFSET +
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IPI_BUFFER_REQ_OFFSET;
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/* Wait until previous interrupt is handled by PMU */
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pm_ipi_wait(proc);
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/* Write payload into IPI buffer */
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for (size_t i = 0; i < PAYLOAD_ARG_CNT; i++) {
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mmio_write_32(buffer_base + offset, payload[i]);
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offset += PAYLOAD_ARG_SIZE;
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}
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/* Generate IPI to PMU */
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mmio_write_32(proc->ipi->base + IPI_TRIG_OFFSET, IPI_PMU_PM_INT_MASK);
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ipi_mb_notify(proc->ipi->apu_ipi_id, proc->ipi->pmu_ipi_id, 1);
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return PM_RET_SUCCESS;
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}
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@ -178,8 +121,6 @@ static enum pm_ret_status pm_ipi_buff_read(const struct pm_proc *proc,
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IPI_BUFFER_TARGET_PMU_OFFSET +
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IPI_BUFFER_RESP_OFFSET;
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pm_ipi_wait(proc);
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/*
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* Read response from IPI buffer
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* buf-0: success or error+reason
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@ -250,17 +191,12 @@ unlock:
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return ret;
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}
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void pm_ipi_irq_enable(void)
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void pm_ipi_irq_enable(const struct pm_proc *proc)
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{
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mmio_write_32(IPI_APU_IER, IPI_APU_IXR_PMU_0_MASK);
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ipi_mb_enable_irq(proc->ipi->apu_ipi_id, proc->ipi->pmu_ipi_id);
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}
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void pm_ipi_irq_disable(void)
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void pm_ipi_irq_clear(const struct pm_proc *proc)
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{
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mmio_write_32(IPI_APU_IDR, IPI_APU_IXR_PMU_0_MASK);
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}
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void pm_ipi_irq_clear(void)
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{
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mmio_write_32(IPI_APU_ISR, IPI_APU_IXR_PMU_0_MASK);
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ipi_mb_ack(proc->ipi->apu_ipi_id, proc->ipi->pmu_ipi_id);
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
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@ -9,7 +9,7 @@
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#include "pm_common.h"
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int pm_ipi_init(void);
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int pm_ipi_init(const struct pm_proc *proc);
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enum pm_ret_status pm_ipi_send(const struct pm_proc *proc,
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uint32_t payload[PAYLOAD_ARG_CNT]);
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@ -17,8 +17,7 @@ enum pm_ret_status pm_ipi_send_sync(const struct pm_proc *proc,
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uint32_t payload[PAYLOAD_ARG_CNT],
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unsigned int *value, size_t count);
|
||||
void pm_ipi_buff_read_callb(unsigned int *value, size_t count);
|
||||
void pm_ipi_irq_enable(void);
|
||||
void pm_ipi_irq_disable(void);
|
||||
void pm_ipi_irq_clear(void);
|
||||
void pm_ipi_irq_enable(const struct pm_proc *proc);
|
||||
void pm_ipi_irq_clear(const struct pm_proc *proc);
|
||||
|
||||
#endif /* _PM_IPI_H_ */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -49,22 +49,25 @@ static struct {
|
|||
*/
|
||||
int pm_setup(void)
|
||||
{
|
||||
int status;
|
||||
int status, ret;
|
||||
|
||||
if (!zynqmp_is_pmu_up())
|
||||
return -ENODEV;
|
||||
|
||||
status = pm_ipi_init();
|
||||
status = pm_ipi_init(primary_proc);
|
||||
|
||||
if (status == 0)
|
||||
if (status >= 0) {
|
||||
INFO("BL31: PM Service Init Complete: API v%d.%d\n",
|
||||
PM_VERSION_MAJOR, PM_VERSION_MINOR);
|
||||
else
|
||||
ret = 0;
|
||||
} else {
|
||||
INFO("BL31: PM Service Init Failed, Error Code %d!\n", status);
|
||||
ret = status;
|
||||
}
|
||||
|
||||
pm_down = status;
|
||||
|
||||
return status;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -163,7 +166,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
|
|||
* Even if we were wrong, it would not enable the IRQ in
|
||||
* the GIC.
|
||||
*/
|
||||
pm_ipi_irq_enable();
|
||||
pm_ipi_irq_enable(primary_proc);
|
||||
SMC_RET1(handle, (uint64_t)ret |
|
||||
((uint64_t)pm_ctx.api_version << 32));
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -8,7 +8,9 @@
|
|||
|
||||
#include <runtime_svc.h>
|
||||
#include <uuid.h>
|
||||
#include "ipi_mailbox_svc.h"
|
||||
#include "pm_svc_main.h"
|
||||
#include "zynqmp_ipi.h"
|
||||
|
||||
/* SMC function IDs for SiP Service queries */
|
||||
#define ZYNQMP_SIP_SVC_CALL_COUNT 0x8200ff00
|
||||
|
|
@ -19,10 +21,12 @@
|
|||
#define SIP_SVC_VERSION_MAJOR 0
|
||||
#define SIP_SVC_VERSION_MINOR 1
|
||||
|
||||
/* These macros are used to identify PM calls from the SMC function ID */
|
||||
/* These macros are used to identify PM, IPI calls from the SMC function ID */
|
||||
#define PM_FID_MASK 0xf000u
|
||||
#define PM_FID_VALUE 0u
|
||||
#define IPI_FID_VALUE 0x1000u
|
||||
#define is_pm_fid(_fid) (((_fid) & PM_FID_MASK) == PM_FID_VALUE)
|
||||
#define is_ipi_fid(_fid) (((_fid) & PM_FID_MASK) == IPI_FID_VALUE)
|
||||
|
||||
/* SiP Service UUID */
|
||||
DEFINE_SVC_UUID(zynqmp_sip_uuid,
|
||||
|
|
@ -63,6 +67,12 @@ uint64_t sip_svc_smc_handler(uint32_t smc_fid,
|
|||
flags);
|
||||
}
|
||||
|
||||
/* Let IPI SMC handler deal with IPI-related requests */
|
||||
if (is_ipi_fid(smc_fid)) {
|
||||
return ipi_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle,
|
||||
flags);
|
||||
}
|
||||
|
||||
switch (smc_fid) {
|
||||
case ZYNQMP_SIP_SVC_CALL_COUNT:
|
||||
/* PM functions + default functions */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,283 @@
|
|||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* Zynq UltraScale+ MPSoC IPI agent registers access management
|
||||
*/
|
||||
|
||||
#include <bakery_lock.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <mmio.h>
|
||||
#include <runtime_svc.h>
|
||||
#include <string.h>
|
||||
#include "zynqmp_ipi.h"
|
||||
#include "../zynqmp_private.h"
|
||||
|
||||
/*********************************************************************
|
||||
* Macros definitions
|
||||
********************************************************************/
|
||||
|
||||
/* IPI registers base address */
|
||||
#define IPI_REGS_BASE 0xFF300000U
|
||||
|
||||
/* IPI registers offsets macros */
|
||||
#define IPI_TRIG_OFFSET 0x00U
|
||||
#define IPI_OBR_OFFSET 0x04U
|
||||
#define IPI_ISR_OFFSET 0x10U
|
||||
#define IPI_IMR_OFFSET 0x14U
|
||||
#define IPI_IER_OFFSET 0x18U
|
||||
#define IPI_IDR_OFFSET 0x1CU
|
||||
|
||||
/* IPI register start offset */
|
||||
#define IPI_REG_BASE(I) (zynqmp_ipi_table[(I)].ipi_reg_base)
|
||||
|
||||
/* IPI register bit mask */
|
||||
#define IPI_BIT_MASK(I) (zynqmp_ipi_table[(I)].ipi_bit_mask)
|
||||
|
||||
/* IPI secure check */
|
||||
#define IPI_SECURE_MASK 0x1U
|
||||
#define IPI_IS_SECURE(I) ((zynqmp_ipi_table[(I)].secure_only & \
|
||||
IPI_SECURE_MASK) ? 1 : 0)
|
||||
|
||||
/*********************************************************************
|
||||
* Struct definitions
|
||||
********************************************************************/
|
||||
|
||||
/* structure to maintain IPI configuration information */
|
||||
struct zynqmp_ipi_config {
|
||||
unsigned int ipi_bit_mask;
|
||||
unsigned int ipi_reg_base;
|
||||
unsigned char secure_only;
|
||||
};
|
||||
|
||||
/* Zynqmp ipi configuration table */
|
||||
const static struct zynqmp_ipi_config zynqmp_ipi_table[] = {
|
||||
/* APU IPI */
|
||||
{
|
||||
.ipi_bit_mask = 0x1,
|
||||
.ipi_reg_base = 0xFF300000,
|
||||
.secure_only = 0,
|
||||
},
|
||||
/* RPU0 IPI */
|
||||
{
|
||||
.ipi_bit_mask = 0x100,
|
||||
.ipi_reg_base = 0xFF310000,
|
||||
.secure_only = 0,
|
||||
},
|
||||
/* RPU1 IPI */
|
||||
{
|
||||
.ipi_bit_mask = 0x200,
|
||||
.ipi_reg_base = 0xFF320000,
|
||||
.secure_only = 0,
|
||||
},
|
||||
/* PMU0 IPI */
|
||||
{
|
||||
.ipi_bit_mask = 0x10000,
|
||||
.ipi_reg_base = 0xFF330000,
|
||||
.secure_only = IPI_SECURE_MASK,
|
||||
},
|
||||
/* PMU1 IPI */
|
||||
{
|
||||
.ipi_bit_mask = 0x20000,
|
||||
.ipi_reg_base = 0xFF331000,
|
||||
.secure_only = IPI_SECURE_MASK,
|
||||
},
|
||||
/* PMU2 IPI */
|
||||
{
|
||||
.ipi_bit_mask = 0x40000,
|
||||
.ipi_reg_base = 0xFF332000,
|
||||
.secure_only = IPI_SECURE_MASK,
|
||||
},
|
||||
/* PMU3 IPI */
|
||||
{
|
||||
.ipi_bit_mask = 0x80000,
|
||||
.ipi_reg_base = 0xFF333000,
|
||||
.secure_only = IPI_SECURE_MASK,
|
||||
},
|
||||
/* PL0 IPI */
|
||||
{
|
||||
.ipi_bit_mask = 0x1000000,
|
||||
.ipi_reg_base = 0xFF340000,
|
||||
.secure_only = 0,
|
||||
},
|
||||
/* PL1 IPI */
|
||||
{
|
||||
.ipi_bit_mask = 0x2000000,
|
||||
.ipi_reg_base = 0xFF350000,
|
||||
.secure_only = 0,
|
||||
},
|
||||
/* PL2 IPI */
|
||||
{
|
||||
.ipi_bit_mask = 0x4000000,
|
||||
.ipi_reg_base = 0xFF360000,
|
||||
.secure_only = 0,
|
||||
},
|
||||
/* PL3 IPI */
|
||||
{
|
||||
.ipi_bit_mask = 0x8000000,
|
||||
.ipi_reg_base = 0xFF370000,
|
||||
.secure_only = 0,
|
||||
},
|
||||
};
|
||||
|
||||
/* is_ipi_mb_within_range() - verify if IPI mailbox is within range
|
||||
*
|
||||
* @local - local IPI ID
|
||||
* @remote - remote IPI ID
|
||||
*
|
||||
* return - 1 if within range, 0 if not
|
||||
*/
|
||||
static inline int is_ipi_mb_within_range(uint32_t local, uint32_t remote)
|
||||
{
|
||||
int ret = 1;
|
||||
uint32_t ipi_total = ARRAY_SIZE(zynqmp_ipi_table);
|
||||
|
||||
if (remote >= ipi_total || local >= ipi_total)
|
||||
ret = 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* ipi_mb_validate() - validate IPI mailbox access
|
||||
*
|
||||
* @local - local IPI ID
|
||||
* @remote - remote IPI ID
|
||||
* @is_secure - indicate if the requester is from secure software
|
||||
*
|
||||
* return - 0 success, negative value for errors
|
||||
*/
|
||||
int ipi_mb_validate(uint32_t local, uint32_t remote, unsigned int is_secure)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (!is_ipi_mb_within_range(local, remote))
|
||||
ret = -EINVAL;
|
||||
else if (IPI_IS_SECURE(local) && !is_secure)
|
||||
ret = -EPERM;
|
||||
else if (IPI_IS_SECURE(remote) && !is_secure)
|
||||
ret = -EPERM;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* ipi_mb_open() - Open IPI mailbox.
|
||||
*
|
||||
* @local - local IPI ID
|
||||
* @remote - remote IPI ID
|
||||
*
|
||||
*/
|
||||
void ipi_mb_open(uint32_t local, uint32_t remote)
|
||||
{
|
||||
mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET,
|
||||
IPI_BIT_MASK(remote));
|
||||
mmio_write_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET,
|
||||
IPI_BIT_MASK(remote));
|
||||
}
|
||||
|
||||
/**
|
||||
* ipi_mb_release() - Open IPI mailbox.
|
||||
*
|
||||
* @local - local IPI ID
|
||||
* @remote - remote IPI ID
|
||||
*
|
||||
*/
|
||||
void ipi_mb_release(uint32_t local, uint32_t remote)
|
||||
{
|
||||
mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET,
|
||||
IPI_BIT_MASK(remote));
|
||||
}
|
||||
|
||||
/**
|
||||
* ipi_mb_enquire_status() - Enquire IPI mailbox status
|
||||
*
|
||||
* @local - local IPI ID
|
||||
* @remote - remote IPI ID
|
||||
*
|
||||
* return - 0 idle, positive value for pending sending or receiving,
|
||||
* negative value for errors
|
||||
*/
|
||||
int ipi_mb_enquire_status(uint32_t local, uint32_t remote)
|
||||
{
|
||||
int ret = 0;
|
||||
uint32_t status;
|
||||
|
||||
status = mmio_read_32(IPI_REG_BASE(local) + IPI_OBR_OFFSET);
|
||||
if (status & IPI_BIT_MASK(remote))
|
||||
ret |= IPI_MB_STATUS_SEND_PENDING;
|
||||
status = mmio_read_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
|
||||
if (status & IPI_BIT_MASK(remote))
|
||||
ret |= IPI_MB_STATUS_RECV_PENDING;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* ipi_mb_notify() - Trigger IPI mailbox notification
|
||||
*
|
||||
* @local - local IPI ID
|
||||
* @remote - remote IPI ID
|
||||
* @is_blocking - if to trigger the notification in blocking mode or not.
|
||||
*
|
||||
* It sets the remote bit in the IPI agent trigger register.
|
||||
*
|
||||
*/
|
||||
void ipi_mb_notify(uint32_t local, uint32_t remote, uint32_t is_blocking)
|
||||
{
|
||||
uint32_t status;
|
||||
|
||||
mmio_write_32(IPI_REG_BASE(local) + IPI_TRIG_OFFSET,
|
||||
IPI_BIT_MASK(remote));
|
||||
if (is_blocking) {
|
||||
do {
|
||||
status = mmio_read_32(IPI_REG_BASE(local) +
|
||||
IPI_OBR_OFFSET);
|
||||
} while (status & IPI_BIT_MASK(remote));
|
||||
}
|
||||
}
|
||||
|
||||
/* ipi_mb_ack() - Ack IPI mailbox notification from the other end
|
||||
*
|
||||
* @local - local IPI ID
|
||||
* @remote - remote IPI ID
|
||||
*
|
||||
* It will clear the remote bit in the isr register.
|
||||
*
|
||||
*/
|
||||
void ipi_mb_ack(uint32_t local, uint32_t remote)
|
||||
{
|
||||
mmio_write_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET,
|
||||
IPI_BIT_MASK(remote));
|
||||
}
|
||||
|
||||
/* ipi_mb_disable_irq() - Disable IPI mailbox notification interrupt
|
||||
*
|
||||
* @local - local IPI ID
|
||||
* @remote - remote IPI ID
|
||||
*
|
||||
* It will mask the remote bit in the idr register.
|
||||
*
|
||||
*/
|
||||
void ipi_mb_disable_irq(uint32_t local, uint32_t remote)
|
||||
{
|
||||
mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET,
|
||||
IPI_BIT_MASK(remote));
|
||||
}
|
||||
|
||||
/* ipi_mb_enable_irq() - Enable IPI mailbox notification interrupt
|
||||
*
|
||||
* @local - local IPI ID
|
||||
* @remote - remote IPI ID
|
||||
*
|
||||
* It will mask the remote bit in the idr register.
|
||||
*
|
||||
*/
|
||||
void ipi_mb_enable_irq(uint32_t local, uint32_t remote)
|
||||
{
|
||||
mmio_write_32(IPI_REG_BASE(local) + IPI_IER_OFFSET,
|
||||
IPI_BIT_MASK(remote));
|
||||
}
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/* ZynqMP IPI management enums and defines */
|
||||
|
||||
#ifndef _ZYNQMP_IPI_H_
|
||||
#define _ZYNQMP_IPI_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*********************************************************************
|
||||
* IPI agent IDs macros
|
||||
********************************************************************/
|
||||
#define IPI_ID_APU 0U
|
||||
#define IPI_ID_RPU0 1U
|
||||
#define IPI_ID_RPU1 2U
|
||||
#define IPI_ID_PMU0 3U
|
||||
#define IPI_ID_PMU1 4U
|
||||
#define IPI_ID_PMU2 5U
|
||||
#define IPI_ID_PMU3 6U
|
||||
#define IPI_ID_PL0 7U
|
||||
#define IPI_ID_PL1 8U
|
||||
#define IPI_ID_PL2 9U
|
||||
#define IPI_ID_PL3 10U
|
||||
|
||||
/*********************************************************************
|
||||
* IPI mailbox status macros
|
||||
********************************************************************/
|
||||
#define IPI_MB_STATUS_IDLE 0
|
||||
#define IPI_MB_STATUS_SEND_PENDING 1
|
||||
#define IPI_MB_STATUS_RECV_PENDING 2
|
||||
|
||||
/*********************************************************************
|
||||
* IPI mailbox call is secure or not macros
|
||||
********************************************************************/
|
||||
#define IPI_MB_CALL_NOTSECURE 0
|
||||
#define IPI_MB_CALL_SECURE 1
|
||||
|
||||
/*********************************************************************
|
||||
* IPI APIs declarations
|
||||
********************************************************************/
|
||||
|
||||
/* Validate IPI mailbox access */
|
||||
int ipi_mb_validate(uint32_t local, uint32_t remote, unsigned int is_secure);
|
||||
|
||||
/* Open the IPI mailbox */
|
||||
void ipi_mb_open(uint32_t local, uint32_t remote);
|
||||
|
||||
/* Release the IPI mailbox */
|
||||
void ipi_mb_release(uint32_t local, uint32_t remote);
|
||||
|
||||
/* Enquire IPI mailbox status */
|
||||
int ipi_mb_enquire_status(uint32_t local, uint32_t remote);
|
||||
|
||||
/* Trigger notification on the IPI mailbox */
|
||||
void ipi_mb_notify(uint32_t local, uint32_t remote, uint32_t is_blocking);
|
||||
|
||||
/* Ack IPI mailbox notification */
|
||||
void ipi_mb_ack(uint32_t local, uint32_t remote);
|
||||
|
||||
/* Disable IPI mailbox notification interrupt */
|
||||
void ipi_mb_disable_irq(uint32_t local, uint32_t remote);
|
||||
|
||||
/* Enable IPI mailbox notification interrupt */
|
||||
void ipi_mb_enable_irq(uint32_t local, uint32_t remote);
|
||||
|
||||
#endif /* _ZYNQMP_IPI_H_ */
|
||||
Loading…
Reference in New Issue