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Tegra: memctrl: platform setup handler functions 

The driver initially contained the setup steps to help Tegra186
and Tegra194 SoCs. In order to support future SoCs and make sure
that the driver remains generic enough, some code should be moved
to SoC.

This patch creates a setup handler for a platform to implement its
initialization sequence.

Change-Id: I8bab7fd07f25e0457ead8e2d2713efe54782a59b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2019-08-26 10:20:53 -07:00
parent 872a1c52b8
commit 08e60f803f
6 changed files with 194 additions and 235 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

71
plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c
View File

@ -32,38 +32,13 @@ static uint64_t video_mem_size_mb;
*/
void tegra_memctrl_setup(void)
{
uint32_t val;
const uint32_t *mc_streamid_override_regs;
uint32_t num_streamid_override_regs;
const mc_streamid_security_cfg_t *mc_streamid_sec_cfgs;
uint32_t num_streamid_sec_cfgs;
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
uint32_t i;
INFO("Tegra Memory Controller (v2)\n");
/* Program the SMMU pagesize */
/* Initialize the System memory management unit */
tegra_smmu_init();
/* Get the settings from the platform */
assert(plat_mc_settings != NULL);
mc_streamid_override_regs = plat_mc_settings->streamid_override_cfg;
num_streamid_override_regs = plat_mc_settings->num_streamid_override_cfgs;
mc_streamid_sec_cfgs = plat_mc_settings->streamid_security_cfg;
num_streamid_sec_cfgs = plat_mc_settings->num_streamid_security_cfgs;
/* Program all the Stream ID overrides */
for (i = 0; i < num_streamid_override_regs; i++)
tegra_mc_streamid_write_32(mc_streamid_override_regs[i],
MC_STREAM_ID_MAX);
/* Program the security config settings for all Stream IDs */
for (i = 0; i < num_streamid_sec_cfgs; i++) {
val = mc_streamid_sec_cfgs[i].override_enable << 16 |
mc_streamid_sec_cfgs[i].override_client_inputs << 8 |
mc_streamid_sec_cfgs[i].override_client_ns_flag << 0;
tegra_mc_streamid_write_32(mc_streamid_sec_cfgs[i].offset, val);
}
/* allow platforms to program custom memory controller settings */
plat_memctrl_setup();
/*
* All requests at boot time, and certain requests during
@ -80,23 +55,6 @@ void tegra_memctrl_setup(void)
*/
tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG,
MC_SMMU_BYPASS_CONFIG_SETTINGS);
assert(tegra_mc_read_32(MC_SMMU_BYPASS_CONFIG)
== MC_SMMU_BYPASS_CONFIG_SETTINGS);
/*
* Re-configure MSS to allow ROC to deal with ordering of the
* Memory Controller traffic. This is needed as the Memory Controller
* boots with MSS having all control, but ROC provides a performance
* boost as compared to MSS.
*/
if (plat_mc_settings->reconfig_mss_clients != NULL) {
plat_mc_settings->reconfig_mss_clients();
}
/* Program overrides for MC transactions */
if (plat_mc_settings->set_txn_overrides != NULL) {
plat_mc_settings->set_txn_overrides();
}
}
/*
@ -104,24 +62,8 @@ void tegra_memctrl_setup(void)
*/
void tegra_memctrl_restore_settings(void)
{
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
assert(plat_mc_settings != NULL);
/*
* Re-configure MSS to allow ROC to deal with ordering of the
* Memory Controller traffic. This is needed as the Memory Controller
* resets during System Suspend with MSS having all control, but ROC
* provides a performance boost as compared to MSS.
*/
if (plat_mc_settings->reconfig_mss_clients != NULL) {
plat_mc_settings->reconfig_mss_clients();
}
/* Program overrides for MC transactions */
if (plat_mc_settings->set_txn_overrides != NULL) {
plat_mc_settings->set_txn_overrides();
}
/* restore platform's memory controller settings */
plat_memctrl_restore();
/* video memory carveout region */
if (video_mem_base != 0ULL) {
@ -176,7 +118,6 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
*/
void tegra_mc_save_context(uint64_t mc_ctx_addr)
{
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
uint32_t i, num_entries = 0;
mc_regs_t *mc_ctx_regs;
const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
@ -186,7 +127,7 @@ void tegra_mc_save_context(uint64_t mc_ctx_addr)
assert((mc_ctx_addr >= tzdram_base) && (mc_ctx_addr <= tzdram_end));
/* get MC context table */
mc_ctx_regs = plat_mc_settings->get_mc_system_suspend_ctx();
mc_ctx_regs = plat_memctrl_get_sys_suspend_ctx();
assert(mc_ctx_regs != NULL);
/*

143
plat/nvidia/tegra/include/drivers/memctrl_v2.h
View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,59 +8,10 @@
#ifndef MEMCTRL_V2_H
#define MEMCTRL_V2_H
#include <arch.h>
#include <tegra_def.h>
#ifndef __ASSEMBLER__
#include <lib/mmio.h>
#include <stdint.h>
/*******************************************************************************
* Structure to hold the transaction override settings to use to override
* client inputs
******************************************************************************/
typedef struct mc_txn_override_cfg {
uint32_t offset;
uint8_t cgid_tag;
} mc_txn_override_cfg_t;
#define mc_make_txn_override_cfg(off, val) \
{ \
.offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \
.cgid_tag = MC_TXN_OVERRIDE_ ## val \
}
/*******************************************************************************
* Structure to hold the Stream ID to use to override client inputs
******************************************************************************/
typedef struct mc_streamid_override_cfg {
uint32_t offset;
uint8_t stream_id;
} mc_streamid_override_cfg_t;
/*******************************************************************************
* Structure to hold the Stream ID Security Configuration settings
******************************************************************************/
typedef struct mc_streamid_security_cfg {
char *name;
uint32_t offset;
int override_enable;
int override_client_inputs;
int override_client_ns_flag;
} mc_streamid_security_cfg_t;
#define OVERRIDE_DISABLE 1U
#define OVERRIDE_ENABLE 0U
#define CLIENT_FLAG_SECURE 0U
#define CLIENT_FLAG_NON_SECURE 1U
#define CLIENT_INPUTS_OVERRIDE 1U
#define CLIENT_INPUTS_NO_OVERRIDE 0U
/*******************************************************************************
* StreamID to indicate no SMMU translations (requests to be steered on the
* SMMU bypass path)
******************************************************************************/
#define MC_STREAM_ID_MAX 0x7FU
/*******************************************************************************
* Memory Controller SMMU Bypass config register
******************************************************************************/
@ -74,15 +26,7 @@ typedef struct mc_streamid_security_cfg {
#define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
#define mc_make_sec_cfg(off, ns, ovrrd, access) \
{ \
.name = # off, \
.offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \
MC_STREAMID_OVERRIDE_CFG_ ## off), \
.override_client_ns_flag = CLIENT_FLAG_ ## ns, \
.override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \
.override_enable = OVERRIDE_ ## access \
}
#ifndef __ASSEMBLY__
#include <assert.h>
@ -91,18 +35,6 @@ typedef struct mc_regs {
uint32_t val;
} mc_regs_t;
#define mc_make_sid_override_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \
.val = 0x00000000U, \
}
#define mc_make_sid_security_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(MC_STREAMID_OVERRIDE_CFG_ ## name), \
.val = 0x00000000U, \
}
#define mc_smmu_bypass_cfg \
{ \
.reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \
@ -121,20 +53,11 @@ typedef struct mc_regs {
.val = 0xFFFFFFFFU, \
}
/*******************************************************************************
* Structure to hold Memory Controller's Configuration settings
******************************************************************************/
typedef struct tegra_mc_settings {
const uint32_t *streamid_override_cfg;
uint32_t num_streamid_override_cfgs;
const mc_streamid_security_cfg_t *streamid_security_cfg;
uint32_t num_streamid_security_cfgs;
const mc_txn_override_cfg_t *txn_override_cfg;
uint32_t num_txn_override_cfgs;
void (*reconfig_mss_clients)(void);
void (*set_txn_overrides)(void);
mc_regs_t* (*get_mc_system_suspend_ctx)(void);
} tegra_mc_settings_t;
#endif /* __ASSEMBLY__ */
#ifndef __ASSEMBLY__
#include <lib/mmio.h>
static inline uint32_t tegra_mc_read_32(uint32_t off)
{
@ -159,52 +82,10 @@ static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val)
}
#endif
#define mc_set_pcfifo_unordered_boot_so_mss(id, client) \
((uint32_t)~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)
void plat_memctrl_setup(void);
#define mc_set_pcfifo_ordered_boot_so_mss(id, client) \
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_ORDERED
#define mc_set_tsa_passthrough(client) \
{ \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
(TSA_CONFIG_STATIC0_CSW_##client##_RESET & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
}
#define mc_set_tsa_w_passthrough(client) \
{ \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
(TSA_CONFIG_STATIC0_CSW_RESET_W & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
}
#define mc_set_tsa_r_passthrough(client) \
{ \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSR_##client, \
(TSA_CONFIG_STATIC0_CSR_RESET_R & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
}
#define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \
{ \
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
MC_TXN_OVERRIDE_##normal_axi_id | \
MC_TXN_OVERRIDE_CONFIG_COH_PATH_##so_dev_override##_SO_DEV | \
MC_TXN_OVERRIDE_CONFIG_COH_PATH_##normal_override##_NORMAL | \
MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \
}
/*******************************************************************************
* Handler to read memory configuration settings
*
* Implemented by SoCs under tegra/soc/txxx
******************************************************************************/
tegra_mc_settings_t *tegra_get_mc_settings(void);
void plat_memctrl_restore(void);
mc_regs_t *plat_memctrl_get_sys_suspend_ctx(void);
/*******************************************************************************
* Handler to save MC settings before "System Suspend" to TZDRAM

115
plat/nvidia/tegra/include/t186/tegra_mc_def.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -282,4 +282,117 @@
#define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 24)
#define MC_CLIENT_HOTRESET_STATUS1 0x974U
#ifndef __ASSEMBLY__
/*******************************************************************************
* Structure to hold the transaction override settings to use to override
* client inputs
******************************************************************************/
typedef struct mc_txn_override_cfg {
uint32_t offset;
uint8_t cgid_tag;
} mc_txn_override_cfg_t;
#define mc_make_txn_override_cfg(off, val) \
{ \
.offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \
.cgid_tag = MC_TXN_OVERRIDE_ ## val \
}
/*******************************************************************************
* Structure to hold the Stream ID to use to override client inputs
******************************************************************************/
typedef struct mc_streamid_override_cfg {
uint32_t offset;
uint8_t stream_id;
} mc_streamid_override_cfg_t;
/*******************************************************************************
* Structure to hold the Stream ID Security Configuration settings
******************************************************************************/
typedef struct mc_streamid_security_cfg {
char *name;
uint32_t offset;
uint32_t override_enable;
uint32_t override_client_inputs;
uint32_t override_client_ns_flag;
} mc_streamid_security_cfg_t;
#define OVERRIDE_DISABLE 1U
#define OVERRIDE_ENABLE 0U
#define CLIENT_FLAG_SECURE 0U
#define CLIENT_FLAG_NON_SECURE 1U
#define CLIENT_INPUTS_OVERRIDE 1U
#define CLIENT_INPUTS_NO_OVERRIDE 0U
/*******************************************************************************
* StreamID to indicate no SMMU translations (requests to be steered on the
* SMMU bypass path)
******************************************************************************/
#define MC_STREAM_ID_MAX 0x7FU
#define mc_make_sec_cfg(off, ns, ovrrd, access) \
{ \
.name = # off, \
.offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \
MC_STREAMID_OVERRIDE_CFG_ ## off), \
.override_client_ns_flag = CLIENT_FLAG_ ## ns, \
.override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \
.override_enable = OVERRIDE_ ## access \
}
#define mc_make_sid_override_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \
.val = 0x00000000U, \
}
#define mc_make_sid_security_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(MC_STREAMID_OVERRIDE_CFG_ ## name), \
.val = 0x00000000U, \
}
#define mc_set_pcfifo_unordered_boot_so_mss(id, client) \
((uint32_t)~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)
#define mc_set_pcfifo_ordered_boot_so_mss(id, client) \
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_ORDERED
#define mc_set_tsa_passthrough(client) \
do { \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
(TSA_CONFIG_STATIC0_CSW_##client##_RESET & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
} while (0)
#define mc_set_tsa_w_passthrough(client) \
do { \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
(TSA_CONFIG_STATIC0_CSW_RESET_W & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
} while (0)
#define mc_set_tsa_r_passthrough(client) \
{ \
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSR_##client, \
(TSA_CONFIG_STATIC0_CSR_RESET_R & \
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
} while (0)
#define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \
do { \
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
MC_TXN_OVERRIDE_##normal_axi_id | \
MC_TXN_OVERRIDE_CONFIG_COH_PATH_##so_dev_override##_SO_DEV | \
MC_TXN_OVERRIDE_CONFIG_COH_PATH_##normal_override##_NORMAL | \
MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \
} while (0)
#endif /* __ASSEMBLY__ */
#endif /* TEGRA_MC_DEF_H */

5
plat/nvidia/tegra/include/tegra_private.h
View File

@ -68,6 +68,11 @@ struct tegra_bl31_params {
image_info_t *bl33_image_info;
};
/*******************************************************************************
* To suppress Coverity MISRA C-2012 Rule 2.2 violations
*******************************************************************************/
#define UNUSED_FUNC_NOP() asm("nop")
/* Declarations for plat_psci_handlers.c */
int32_t tegra_soc_validate_power_state(uint32_t power_state,
psci_power_state_t *req_state);

77
plat/nvidia/tegra/soc/t186/plat_memctrl.c
View File

@ -402,16 +402,8 @@ static void tegra186_memctrl_reconfig_mss_clients(void)
static void tegra186_memctrl_set_overrides(void)
{
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
const mc_txn_override_cfg_t *mc_txn_override_cfgs;
uint32_t num_txn_override_cfgs;
uint32_t i, val;
/* Get the settings from the platform */
assert(plat_mc_settings != NULL);
mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg;
num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs;
/*
* Set the MC_TXN_OVERRIDE registers for write clients.
*/
@ -443,11 +435,11 @@ static void tegra186_memctrl_set_overrides(void)
/*
* Settings for Tegra186 silicon rev. A02 and onwards.
*/
for (i = 0; i < num_txn_override_cfgs; i++) {
val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset);
for (i = 0; i < ARRAY_SIZE(tegra186_txn_override_cfgs); i++) {
val = tegra_mc_read_32(tegra186_txn_override_cfgs[i].offset);
val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(mc_txn_override_cfgs[i].offset,
val | mc_txn_override_cfgs[i].cgid_tag);
tegra_mc_write_32(tegra186_txn_override_cfgs[i].offset,
val | tegra186_txn_override_cfgs[i].cgid_tag);
}
}
}
@ -609,7 +601,7 @@ static __attribute__((aligned(16))) mc_regs_t tegra186_mc_context[] = {
/*******************************************************************************
* Handler to return the pointer to the MC's context struct
******************************************************************************/
static mc_regs_t *tegra186_get_mc_system_suspend_ctx(void)
mc_regs_t *plat_memctrl_get_sys_suspend_ctx(void)
{
/* index of _END_OF_TABLE_ */
tegra186_mc_context[0].val = (uint32_t)(ARRAY_SIZE(tegra186_mc_context)) - 1U;
@ -617,27 +609,52 @@ static mc_regs_t *tegra186_get_mc_system_suspend_ctx(void)
return tegra186_mc_context;
}
/*******************************************************************************
* Struct to hold the memory controller settings
******************************************************************************/
static tegra_mc_settings_t tegra186_mc_settings = {
.streamid_override_cfg = tegra186_streamid_override_regs,
.num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_streamid_override_regs),
.streamid_security_cfg = tegra186_streamid_sec_cfgs,
.num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra186_streamid_sec_cfgs),
.txn_override_cfg = tegra186_txn_override_cfgs,
.num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_txn_override_cfgs),
.reconfig_mss_clients = tegra186_memctrl_reconfig_mss_clients,
.set_txn_overrides = tegra186_memctrl_set_overrides,
.get_mc_system_suspend_ctx = tegra186_get_mc_system_suspend_ctx,
};
void plat_memctrl_setup(void)
{
uint32_t val;
unsigned int i;
/* Program all the Stream ID overrides */
for (i = 0U; i < ARRAY_SIZE(tegra186_streamid_override_regs); i++) {
tegra_mc_streamid_write_32(tegra186_streamid_override_regs[i],
MC_STREAM_ID_MAX);
}
/* Program the security config settings for all Stream IDs */
for (i = 0U; i < ARRAY_SIZE(tegra186_streamid_sec_cfgs); i++) {
val = (tegra186_streamid_sec_cfgs[i].override_enable << 16) |
(tegra186_streamid_sec_cfgs[i].override_client_inputs << 8) |
(tegra186_streamid_sec_cfgs[i].override_client_ns_flag << 0);
tegra_mc_streamid_write_32(tegra186_streamid_sec_cfgs[i].offset, val);
}
/*
* Re-configure MSS to allow ROC to deal with ordering of the
* Memory Controller traffic. This is needed as the Memory Controller
* boots with MSS having all control, but ROC provides a performance
* boost as compared to MSS.
*/
tegra186_memctrl_reconfig_mss_clients();
/* Program overrides for MC transactions */
tegra186_memctrl_set_overrides();
}
/*******************************************************************************
* Handler to return the pointer to the memory controller's settings struct
* Handler to restore platform specific settings to the memory controller
******************************************************************************/
tegra_mc_settings_t *tegra_get_mc_settings(void)
void plat_memctrl_restore(void)
{
return &tegra186_mc_settings;
/*
* Re-configure MSS to allow ROC to deal with ordering of the
* Memory Controller traffic. This is needed as the Memory Controller
* boots with MSS having all control, but ROC provides a performance
* boost as compared to MSS.
*/
tegra186_memctrl_reconfig_mss_clients();
/* Program overrides for MC transactions */
tegra186_memctrl_set_overrides();
}
/*******************************************************************************

18
plat/nvidia/tegra/soc/t194/plat_memctrl.c
View File

@ -10,6 +10,7 @@
#include <memctrl_v2.h>
#include <tegra_mc_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
/*******************************************************************************
* Array to hold MC context for Tegra194
@ -23,7 +24,7 @@ static __attribute__((aligned(16))) mc_regs_t tegra194_mc_context[] = {
/*******************************************************************************
* Handler to return the pointer to the MC's context struct
******************************************************************************/
static mc_regs_t *tegra194_get_mc_system_suspend_ctx(void)
mc_regs_t *plat_memctrl_get_sys_suspend_ctx(void)
{
/* index of _END_OF_TABLE_ */
tegra194_mc_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_mc_context) - 1U;
@ -32,18 +33,19 @@ static mc_regs_t *tegra194_get_mc_system_suspend_ctx(void)
}
/*******************************************************************************
* Struct to hold the memory controller settings
* Handler to restore platform specific settings to the memory controller
******************************************************************************/
static tegra_mc_settings_t tegra194_mc_settings = {
.get_mc_system_suspend_ctx = tegra194_get_mc_system_suspend_ctx
};
void plat_memctrl_restore(void)
{
UNUSED_FUNC_NOP(); /* do nothing */
}
/*******************************************************************************
* Handler to return the pointer to the memory controller's settings struct
* Handler to program platform specific settings to the memory controller
******************************************************************************/
tegra_mc_settings_t *tegra_get_mc_settings(void)
void plat_memctrl_setup(void)
{
return &tegra194_mc_settings;
UNUSED_FUNC_NOP(); /* do nothing */
}
/*******************************************************************************