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Convert arm_setup_page_tables into a generic helper 

This function is not related to Arm platforms and can be reused by other
platforms if needed.

Change-Id: Ia9c328ce57ce7e917b825a9e09a42b0abb1a53e8
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This commit is contained in:
Roberto Vargas 2018-10-19 16:44:18 +01:00 committed by Antonio Nino Diaz
parent 03987d01e9
commit 0916c38dec
16 changed files with 58 additions and 58 deletions
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5
include/common/bl_common.h
View File

@ -193,6 +193,11 @@ extern const char version_string[];
void print_entry_point_info(const entry_point_info_t *ep_info);
uintptr_t page_align(uintptr_t value, unsigned dir);
struct mmap_region;
void setup_page_tables(const struct mmap_region *bl_regions,
const struct mmap_region *plat_regions);
#endif /*__ASSEMBLY__*/
#endif /* __BL_COMMON_H__ */

6
include/plat/arm/common/plat_arm.h
View File

@ -66,12 +66,6 @@ typedef struct arm_tzc_regions_info {
<= MAX_MMAP_REGIONS, \
assert_max_mmap_regions);
/*
* Utility functions common to ARM standard platforms
*/
void arm_setup_page_tables(const mmap_region_t bl_regions[],
const mmap_region_t plat_regions[]);
void arm_setup_romlib(void);
#if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32))

4
plat/arm/board/fvp/fvp_common.c
View File

@ -53,8 +53,8 @@ arm_config_t arm_config;
/*
* Table of memory regions for various BL stages to map using the MMU.
* This doesn't include Trusted SRAM as arm_setup_page_tables() already
* takes care of mapping it.
* This doesn't include Trusted SRAM as setup_page_tables() already takes care
* of mapping it.
*
* The flash needs to be mapped as writable in order to erase the FIP's Table of
* Contents in case of unrecoverable error (see plat_error_handler()).

4
plat/arm/board/juno/juno_common.c
View File

@ -8,8 +8,8 @@
/*
* Table of memory regions for different BL stages to map using the MMU.
* This doesn't include Trusted SRAM as arm_setup_page_tables() already
* takes care of mapping it.
* This doesn't include Trusted SRAM as setup_page_tables() already takes care
* of mapping it.
*/
#ifdef IMAGE_BL1
const mmap_region_t plat_arm_mmap[] = {

2
plat/arm/common/arm_bl1_setup.c
View File

@ -123,7 +123,7 @@ void arm_bl1_plat_arch_setup(void)
{0}
};
arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
setup_page_tables(bl_regions, plat_arm_get_mmap());
#ifdef AARCH32
enable_mmu_svc_mon(0);
#else

2
plat/arm/common/arm_bl2_el3_setup.c
View File

@ -79,7 +79,7 @@ void arm_bl2_el3_plat_arch_setup(void)
{0}
};
arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
setup_page_tables(bl_regions, plat_arm_get_mmap());
#ifdef AARCH32
enable_mmu_svc_mon(0);

2
plat/arm/common/arm_bl2_setup.c
View File

@ -125,7 +125,7 @@ void arm_bl2_plat_arch_setup(void)
{0}
};
arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
setup_page_tables(bl_regions, plat_arm_get_mmap());
#ifdef AARCH32
enable_mmu_svc_mon(0);

2
plat/arm/common/arm_bl2u_setup.c
View File

@ -80,7 +80,7 @@ void arm_bl2u_plat_arch_setup(void)
{0}
};
arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
setup_page_tables(bl_regions, plat_arm_get_mmap());
#ifdef AARCH32
enable_mmu_svc_mon(0);

2
plat/arm/common/arm_bl31_setup.c
View File

@ -302,7 +302,7 @@ void __init arm_bl31_plat_arch_setup(void)
{0}
};
arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
setup_page_tables(bl_regions, plat_arm_get_mmap());
enable_mmu_el3(0);

36
plat/arm/common/arm_common.c
View File

@ -32,42 +32,6 @@ void arm_setup_romlib(void)
#endif
}
/*
* Set up the page tables for the generic and platform-specific memory regions.
* The size of the Trusted SRAM seen by the BL image must be specified as well
* as an array specifying the generic memory regions which can be;
* - Code section;
* - Read-only data section;
* - Init code section, if applicable
* - Coherent memory region, if applicable.
*/
void __init arm_setup_page_tables(const mmap_region_t bl_regions[],
const mmap_region_t plat_regions[])
{
#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
const mmap_region_t *regions = bl_regions;
while (regions->size != 0U) {
VERBOSE("Region: 0x%lx - 0x%lx has attributes 0x%x\n",
regions->base_va,
(regions->base_va + regions->size),
regions->attr);
regions++;
}
#endif
/*
* Map the Trusted SRAM with appropriate memory attributes.
* Subsequent mappings will adjust the attributes for specific regions.
*/
mmap_add(bl_regions);
/* Now (re-)map the platform-specific memory regions */
mmap_add(plat_regions);
/* Create the page tables to reflect the above mappings */
init_xlat_tables();
}
uintptr_t plat_get_ns_image_entrypoint(void)
{
#ifdef PRELOADED_BL33_BASE

2
plat/arm/common/sp_min/arm_sp_min_setup.c
View File

@ -208,7 +208,7 @@ void sp_min_plat_arch_setup(void)
{0}
};
arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
setup_page_tables(bl_regions, plat_arm_get_mmap());
enable_mmu_svc_mon(0);
}

2
plat/arm/common/tsp/arm_tsp_setup.c
View File

@ -85,6 +85,6 @@ void tsp_plat_arch_setup(void)
{0}
};
arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
setup_page_tables(bl_regions, plat_arm_get_mmap());
enable_mmu_el1(0);
}

37
plat/common/plat_bl_common.c
View File

@ -73,3 +73,40 @@ int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
return 0;
}
#endif /* TRUSTED_BOARD_BOOT */
/*
* Set up the page tables for the generic and platform-specific memory regions.
* The size of the Trusted SRAM seen by the BL image must be specified as well
* as an array specifying the generic memory regions which can be;
* - Code section;
* - Read-only data section;
* - Init code section, if applicable
* - Coherent memory region, if applicable.
*/
void __init setup_page_tables(const mmap_region_t *bl_regions,
const mmap_region_t *plat_regions)
{
#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
const mmap_region_t *regions = bl_regions;
while (regions->size != 0U) {
VERBOSE("Region: 0x%lx - 0x%lx has attributes 0x%x\n",
regions->base_va,
regions->base_va + regions->size,
regions->attr);
regions++;
}
#endif
/*
* Map the Trusted SRAM with appropriate memory attributes.
* Subsequent mappings will adjust the attributes for specific regions.
*/
mmap_add(bl_regions);
/* Now (re-)map the platform-specific memory regions */
mmap_add(plat_regions);
/* Create the page tables to reflect the above mappings */
init_xlat_tables();
}

2
plat/ti/k3/common/k3_bl31_setup.c
View File

@ -108,7 +108,7 @@ void bl31_plat_arch_setup(void)
{0}
};
arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
setup_page_tables(bl_regions, plat_arm_get_mmap());
enable_mmu_el3(0);
}

4
plat/xilinx/zynqmp/bl31_zynqmp_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -193,6 +193,6 @@ void bl31_plat_arch_setup(void)
{0}
};
arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
setup_page_tables(bl_regions, plat_arm_get_mmap());
enable_mmu_el3(0);
}

4
plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -57,6 +57,6 @@ void tsp_plat_arch_setup(void)
{0}
};
arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
setup_page_tables(bl_regions, plat_arm_get_mmap());
enable_mmu_el1(0);
}