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plat/intel: Fix SMPLSEL for MMC 

MMC sample select needs to be set properly so that DWMMC clock can be
driven to 50Mhz

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: I4a1dde4f6a1e78a36940c57a7a5b162be0bd443a
This commit is contained in:
Tien Hock, Loh 2019-07-09 13:17:04 +08:00
parent 2cbeee4d51
commit 0943ea379f
2 changed files with 8 additions and 0 deletions
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5
plat/intel/soc/stratix10/include/s10_system_manager.h
View File

@ -59,6 +59,11 @@
#define S10_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
#define S10_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
#define S10_SYSMGR_CORE(x) (0xffd12000 + (x))
#define SYSMGR_MMC 0x28
#define SYSMGR_MMC_DRVSEL(x) (((x) & 0x7) << 0)
#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
void enable_nonsecure_access(void);

3
plat/intel/soc/stratix10/soc/s10_system_manager.c
View File

@ -86,5 +86,8 @@ void enable_nonsecure_access(void)
mmio_clrbits_32(S10_CCU_NOC_CPU0_RAMSPACE0_0, 0x03);
mmio_clrbits_32(S10_CCU_NOC_IOM_RAMSPACE0_0, 0x03);
mmio_write_32(S10_SYSMGR_CORE(SYSMGR_MMC), SYSMGR_MMC_DRVSEL(3));
}