commit
0a665ed5d1
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@ -0,0 +1,11 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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/* compatible string */
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compatible = "arm,sgi575";
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};
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@ -0,0 +1,14 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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/* Platform Config */
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compatible = "arm,tb_fw";
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hw_config_addr = <0x0 0xFEF00000>;
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hw_config_max_size = <0x0100000>;
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};
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@ -30,7 +30,8 @@ BL1_SOURCES += ${INTERCONNECT_SOURCES} \
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${CSS_ENT_BASE}/sgi_bl1_setup.c \
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${CSS_ENT_BASE}/sgi_plat_config.c
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BL2_SOURCES += ${CSS_ENT_BASE}/sgi_security.c
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BL2_SOURCES += ${CSS_ENT_BASE}/sgi_security.c \
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${CSS_ENT_BASE}/sgi_image_load.c
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BL31_SOURCES += ${ENT_CPU_SOURCES} \
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${INTERCONNECT_SOURCES} \
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@ -39,6 +40,19 @@ BL31_SOURCES += ${ENT_CPU_SOURCES} \
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${CSS_ENT_BASE}/sgi_topology.c \
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${CSS_ENT_BASE}/sgi_plat_config.c
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# Add the FDT_SOURCES and options for Dynamic Config
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FDT_SOURCES += ${CSS_ENT_BASE}/fdts/${PLAT}_tb_fw_config.dts
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TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
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# Add the TB_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
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FDT_SOURCES += ${CSS_ENT_BASE}/fdts/${PLAT}.dts
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HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
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# Add the HW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config))
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$(eval $(call add_define,SGI_PLAT))
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override CSS_LOAD_SCP_IMAGES := 0
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@ -12,23 +12,8 @@
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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uint32_t plat_version;
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bl_params_node_t *bl_params;
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bl_params = ((bl_params_t *)arg0)->head;
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/* Initialize the platform configuration structure */
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plat_config_init();
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while (bl_params) {
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if (bl_params->image_id == BL33_IMAGE_ID) {
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plat_version = mmio_read_32(SSC_VERSION);
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bl_params->ep_info->args.arg2 = plat_version;
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break;
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}
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bl_params = bl_params->next_params_info;
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}
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arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
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}
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@ -0,0 +1,87 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <debug.h>
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#include <desc_image_load.h>
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#include <libfdt.h>
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#include <platform.h>
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/*******************************************************************************
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* This function inserts Platform information via device tree nodes as,
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* system-id {
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* platform-id = <0>;
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* }
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******************************************************************************/
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static int plat_sgi_append_config_node(void)
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{
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bl_mem_params_node_t *mem_params;
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void *fdt;
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int nodeoffset, err;
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unsigned int platid = 0;
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char *platform_name;
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mem_params = get_bl_mem_params_node(HW_CONFIG_ID);
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if (mem_params == NULL) {
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ERROR("HW CONFIG base address is NULL");
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return -1;
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}
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fdt = (void *)(mem_params->image_info.image_base);
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/* Check the validity of the fdt */
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if (fdt_check_header(fdt) != 0) {
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ERROR("Invalid HW_CONFIG DTB passed\n");
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return -1;
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}
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platform_name = (char *)fdt_getprop(fdt, 0, "compatible", NULL);
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if (strcmp(platform_name, "arm,sgi575") == 0) {
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platid = mmio_read_32(SSC_VERSION);
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} else {
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WARN("Invalid platform \n");
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return -1;
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}
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/* Increase DTB blob by 512 byte */
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err = fdt_open_into(fdt, fdt, mem_params->image_info.image_size + 512);
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if (err < 0) {
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ERROR("Failed to open HW_CONFIG DTB\n");
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return -1;
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}
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/* Create "/system-id" node */
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nodeoffset = fdt_add_subnode(fdt, 0, "system-id");
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if (nodeoffset < 0) {
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ERROR("Failed to add node system-id\n");
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return -1;
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}
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err = fdt_setprop_u32(fdt, nodeoffset, "platform-id", platid);
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if (err < 0) {
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ERROR("Failed to add node platform-id\n");
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return -1;
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}
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return 0;
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}
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/*******************************************************************************
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* This function returns the list of executable images.
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******************************************************************************/
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bl_params_t *plat_get_next_bl_params(void)
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{
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int ret;
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bl_params_t *next_bl_params;
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ret = plat_sgi_append_config_node();
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if (ret != 0)
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panic();
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next_bl_params = get_next_bl_params_from_mem_params_desc();
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populate_next_bl_params_config(next_bl_params);
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return next_bl_params;
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}
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@ -72,50 +72,3 @@ const mmap_region_t plat_arm_mmap[] = {
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#endif
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ARM_CASSERT_MMAP
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/*
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* Set up the page tables for the generic and platform-specific memory regions.
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* The extents of the generic memory regions are specified by the function
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* arguments and consist of:
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* - Trusted SRAM seen by the BL image;
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* - Code section;
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* - Read-only data section;
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* - Coherent memory region, if applicable.
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*/
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#if IMAGE_BL1
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void bl1_plat_arch_setup(void)
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{
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arm_setup_page_tables(ARM_BL_RAM_BASE,
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ARM_BL_RAM_SIZE,
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BL_CODE_BASE,
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BL1_CODE_END,
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BL1_RO_DATA_BASE,
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BL1_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL1_COHERENT_RAM_BASE,
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BL1_COHERENT_RAM_LIMIT
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#endif /* USE_COHERENT_MEM */
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);
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enable_mmu_el3(0);
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}
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#endif /* IMAGE_BL1 */
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#if IMAGE_BL2
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void bl2_plat_arch_setup(void)
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{
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arm_setup_page_tables(BL2_BASE,
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BL2_LIMIT-BL2_BASE,
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BL_CODE_BASE,
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BL_CODE_END,
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BL_RO_DATA_BASE,
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BL_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL2_COHERENT_RAM_BASE,
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BL2_COHERENT_RAM_LIMIT
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#endif /* USE_COHERENT_MEM */
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);
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enable_mmu_el1(0);
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}
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#endif /* IMAGE_BL2 */
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Reference in New Issue