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plat/marvell/a8k: add Globalscale Mochabin support 

Add support for Globalscale MOCHAbin board.

Its based on Armada 7040 SoC and ships in multiple DRAM options:
* 2GB DDR4 (1CS)
* 4GB DDR4 (1CS)
* 8GB DDR4 (2CS)

Since it ships in multiple DRAM configurations, an
Armada 3k style DDR_TOPOLOGY variable is added.
Currently, this only has effect on the MOCHAbin, but
I expect more boards with multiple DRAM sizes to be
supported.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Change-Id: I8a1ec9268fed34f6a81c5cbf1e891f638d461305
This commit is contained in:
Robert Marko 2021-10-11 16:25:49 +02:00
parent fcfecdaf2e
commit 0a6e2147e7
No known key found for this signature in database
GPG Key ID: 66D805C09F36AFA5
7 changed files with 509 additions and 0 deletions
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11
docs/plat/marvell/armada/build.rst
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@ -58,6 +58,7 @@ There are several build options:
- a3700 - A3720 DB, EspressoBin and Turris MOX
- a70x0
- a70x0_amc - AMC board
- a70x0_mochabin - Globalscale MOCHAbin
- a80x0
- a80x0_mcbin - MacchiatoBin
- a80x0_puzzle - IEI Puzzle-M801
@ -150,6 +151,16 @@ A7K/8K/CN913x specific build options:
Specify path to the MSS fimware image binary which will run on Cortex-M3 coprocessor.
It is available in Marvell binaries-marvell git repository. Required when ``MSS_SUPPORT=1``.
Globalscale MOCHAbin specific build options:
- DDR_TOPOLOGY
The DDR topology map index/name, default is 0.
Supported Options:
- 0 - DDR4 1CS 2GB
- 1 - DDR4 1CS 4GB
- 2 - DDR4 2CS 8GB
Armada37x0 specific build options:

227
plat/marvell/armada/a8k/a70x0_mochabin/board/dram_port.c Normal file
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@ -0,0 +1,227 @@
/*
* Copyright (C) 2021 Sartura Ltd.
* Copyright (C) 2021 Globalscale technologies, Inc.
* Copyright (C) 2021 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#include <arch_helpers.h>
#include <common/debug.h>
#include <mv_ddr_if.h>
#include <plat_marvell.h>
/*
* This function may modify the default DRAM parameters
* based on information received from SPD or bootloader
* configuration located on non volatile storage
*/
void plat_marvell_dram_update_topology(void)
{
}
/*
* This struct provides the DRAM training code with
* the appropriate board DRAM configuration
*/
#if DDR_TOPOLOGY == 0
static struct mv_ddr_topology_map board_topology_map_2g = {
/* 1CS 4Gb x4 devices of Samsung K4A4G085WF */
DEBUG_LEVEL_ERROR,
0x1, /* active interfaces */
/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
{ { { {0x1, 0x2, 0, 0},
{0x1, 0x2, 0, 0},
{0x1, 0x2, 0, 0},
{0x1, 0x2, 0, 0},
{0x1, 0x2, 0, 0},
{0x1, 0x2, 0, 0},
{0x1, 0x2, 0, 0},
{0x1, 0x2, 0, 0},
{0x1, 0x2, 0, 0} },
SPEED_BIN_DDR_2400R, /* speed_bin */
MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
MV_DDR_DIE_CAP_4GBIT, /* die capacity */
MV_DDR_FREQ_SAR, /* frequency */
0, 0, /* cas_l, cas_wl */
MV_DDR_TEMP_LOW} }, /* temperature */
BUS_MASK_32BIT, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
NOT_COMBINED, /* ddr twin-die combined*/
{ {0} }, /* raw spd data */
{0}, /* timing parameters */
{ /* electrical configuration */
{ /* memory electrical configuration */
MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
{
MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */
},
{
MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */
MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */
},
MV_DDR_DIC_RZQ_DIV7 /* dic */
},
{ /* phy electrical configuration */
MV_DDR_OHM_30, /* data_drv_p */
MV_DDR_OHM_30, /* data_drv_n */
MV_DDR_OHM_30, /* ctrl_drv_p */
MV_DDR_OHM_30, /* ctrl_drv_n */
{
MV_DDR_OHM_60, /* odt_p 1cs */
MV_DDR_OHM_120 /* odt_p 2cs */
},
{
MV_DDR_OHM_60, /* odt_n 1cs */
MV_DDR_OHM_120 /* odt_n 2cs */
},
},
{ /* mac electrical configuration */
MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
},
}
};
#endif
#if DDR_TOPOLOGY == 1
static struct mv_ddr_topology_map board_topology_map_4g = {
/* 1CS 8Gb x4 devices of Samsung K4A8G085WC-BCTD */
DEBUG_LEVEL_ERROR,
0x1, /* active interfaces */
/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
{ { { {0x1, 0x2, 0, 0},
{0x1, 0x2, 0, 0},
{0x1, 0x2, 0, 0},
{0x1, 0x2, 0, 0},
{0x1, 0x2, 0, 0},
{0x1, 0x2, 0, 0},
{0x1, 0x2, 0, 0},
{0x1, 0x2, 0, 0},
{0x1, 0x2, 0, 0} },
SPEED_BIN_DDR_2400R, /* speed_bin */
MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
MV_DDR_DIE_CAP_8GBIT, /* die capacity */
MV_DDR_FREQ_SAR, /* frequency */
0, 0, /* cas_l, cas_wl */
MV_DDR_TEMP_LOW} }, /* temperature */
BUS_MASK_32BIT, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
NOT_COMBINED, /* ddr twin-die combined*/
{ {0} }, /* raw spd data */
{0}, /* timing parameters */
{ /* electrical configuration */
{ /* memory electrical configuration */
MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
{
MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */
},
{
MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */
MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */
},
MV_DDR_DIC_RZQ_DIV7 /* dic */
},
{ /* phy electrical configuration */
MV_DDR_OHM_30, /* data_drv_p */
MV_DDR_OHM_30, /* data_drv_n */
MV_DDR_OHM_30, /* ctrl_drv_p */
MV_DDR_OHM_30, /* ctrl_drv_n */
{
MV_DDR_OHM_60, /* odt_p 1cs */
MV_DDR_OHM_120 /* odt_p 2cs */
},
{
MV_DDR_OHM_60, /* odt_n 1cs */
MV_DDR_OHM_120 /* odt_n 2cs */
},
},
{ /* mac electrical configuration */
MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
},
}
};
#endif
#if DDR_TOPOLOGY == 2
static struct mv_ddr_topology_map board_topology_map_8g = {
/* 2CS 8Gb x8 devices of Micron MT40A1G8WE-083E IT */
DEBUG_LEVEL_ERROR,
0x1, /* active interfaces */
/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
{ { { {0x3, 0x2, 0, 0},
{0x3, 0x2, 0, 0},
{0x3, 0x2, 0, 0},
{0x3, 0x2, 0, 0},
{0x3, 0x2, 0, 0},
{0x3, 0x2, 0, 0},
{0x3, 0x2, 0, 0},
{0x3, 0x2, 0, 0},
{0x3, 0x2, 0, 0} },
SPEED_BIN_DDR_2400R, /* speed_bin */
MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
MV_DDR_DIE_CAP_8GBIT, /* die capacity */
MV_DDR_FREQ_SAR, /* frequency */
0, 0, /* cas_l, cas_wl */
MV_DDR_TEMP_LOW} }, /* temperature */
BUS_MASK_32BIT, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
NOT_COMBINED, /* ddr twin-die combined*/
{ {0} }, /* raw spd data */
{0}, /* timing parameters */
{ /* electrical configuration */
{ /* memory electrical configuration */
MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
{
MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */
},
{
MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */
MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */
},
MV_DDR_DIC_RZQ_DIV7 /* dic */
},
{ /* phy electrical configuration */
MV_DDR_OHM_30, /* data_drv_p */
MV_DDR_OHM_30, /* data_drv_n */
MV_DDR_OHM_30, /* ctrl_drv_p */
MV_DDR_OHM_30, /* ctrl_drv_n */
{
MV_DDR_OHM_60, /* odt_p 1cs */
MV_DDR_OHM_120 /* odt_p 2cs */
},
{
MV_DDR_OHM_60, /* odt_n 1cs */
MV_DDR_OHM_120 /* odt_n 2cs */
},
},
{ /* mac electrical configuration */
MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
},
}
};
#endif
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
{
/* a70x0_mochabin board supports 3 DDR4 models (2G/1CS, 4G/1CS, 8G/2CS) */
#if DDR_TOPOLOGY == 0
return &board_topology_map_2g;
#elif DDR_TOPOLOGY == 1
return &board_topology_map_4g;
#elif DDR_TOPOLOGY == 2
return &board_topology_map_8g;
#else
#error "Unknown DDR topology"
#endif
}

145
plat/marvell/armada/a8k/a70x0_mochabin/board/marvell_plat_config.c Normal file
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@ -0,0 +1,145 @@
/*
* Copyright (C) 2021 Sartura Ltd.
* Copyright (C) 2021 Globalscale technologies, Inc.
* Copyright (C) 2021 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#include <armada_common.h>
/*
* If bootrom is currently at BLE there's no need to include the memory
* maps structure at this point
*/
#include <mvebu_def.h>
#ifndef IMAGE_BLE
/*****************************************************************************
* AMB Configuration
*****************************************************************************
*/
struct addr_map_win amb_memory_map[] = {
/* CP0 SPI1 CS0 Direct Mode access */
{0xf900, 0x1000000, AMB_SPI1_CS0_ID},
};
int marvell_get_amb_memory_map(struct addr_map_win **win,
uint32_t *size, uintptr_t base)
{
*win = amb_memory_map;
if (*win == NULL)
*size = 0;
else
*size = ARRAY_SIZE(amb_memory_map);
return 0;
}
#endif
/*****************************************************************************
* IO_WIN Configuration
*****************************************************************************
*/
struct addr_map_win io_win_memory_map[] = {
#ifndef IMAGE_BLE
/* MCI 0 indirect window */
{MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID},
/* MCI 1 indirect window */
{MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID},
#endif
};
uint32_t marvell_get_io_win_gcr_target(int ap_index)
{
return PIDI_TID;
}
int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win,
uint32_t *size)
{
*win = io_win_memory_map;
if (*win == NULL)
*size = 0;
else
*size = ARRAY_SIZE(io_win_memory_map);
return 0;
}
#ifndef IMAGE_BLE
/*****************************************************************************
* IOB Configuration
*****************************************************************************
*/
struct addr_map_win iob_memory_map[] = {
/* PEX1_X1 window */
{0x00000000f7000000, 0x1000000, PEX1_TID},
/* PEX2_X1 window */
{0x00000000f8000000, 0x1000000, PEX2_TID},
{0x00000000c0000000, 0x30000000, PEX2_TID},
{0x0000000800000000, 0x100000000, PEX2_TID},
/* PEX0_X4 window */
{0x00000000f6000000, 0x1000000, PEX0_TID},
/* SPI1_CS0 (RUNIT) window */
{0x00000000f9000000, 0x1000000, RUNIT_TID},
};
int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size,
uintptr_t base)
{
*win = iob_memory_map;
*size = ARRAY_SIZE(iob_memory_map);
return 0;
}
#endif
/*****************************************************************************
* CCU Configuration
*****************************************************************************
*/
struct addr_map_win ccu_memory_map[] = { /* IO window */
#ifdef IMAGE_BLE
{0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
#else
#if LLC_SRAM
/* This entry is prepared for OP-TEE OS that enables the LLC SRAM
* and changes the window target to SRAM_TID.
*/
{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
#endif
{0x00000000f2000000, 0xe000000, IO_0_TID},
{0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
{0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
#endif
};
uint32_t marvell_get_ccu_gcr_target(int ap)
{
return DRAM_0_TID;
}
int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win,
uint32_t *size)
{
*win = ccu_memory_map;
*size = ARRAY_SIZE(ccu_memory_map);
return 0;
}
#ifdef IMAGE_BLE
/*****************************************************************************
* SKIP IMAGE Configuration
*****************************************************************************
*/
#if PLAT_RECOVERY_IMAGE_ENABLE
void *plat_marvell_get_skip_image_data(void)
{
/* No recovery button on a70x0_mochabin board */
return NULL;
}
#endif
#endif

87
plat/marvell/armada/a8k/a70x0_mochabin/board/phy-porting-layer.h Normal file
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@ -0,0 +1,87 @@
/*
* Copyright (C) 2021 Sartura Ltd.
* Copyright (C) 2021 Globalscale technologies, Inc.
* Copyright (C) 2021 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#ifndef __PHY_PORTING_LAYER_H
#define __PHY_PORTING_LAYER_H
#define MAX_LANE_NR 6
static const struct xfi_params
xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
/* AP0 */
{
/* CP 0 */
{
{ 0 }, /* Comphy0 */
{ 0 }, /* Comphy1 */
{ 0 }, /* Comphy2 */
{ 0 }, /* Comphy3 */
{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, .align90 = 0x60,
.g1_dfe_res = 0x1, .g1_amp = 0x1c, .g1_emph = 0xe,
.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1, .g1_tx_emph_en = 0x1,
.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
.valid = 1 }, /* Comphy4 */
{ 0 }, /* Comphy5 */
},
},
};
static const struct sata_params
sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
/* AP0 */
{
/* CP 0 */
{
{ 0 }, /* Comphy0 */
{ 0 }, /* Comphy1 */
{ .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
.g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
.g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1,
.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1, .g3_tx_amp_adj = 0x1,
.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0, .g3_tx_emph_en = 0x0,
.g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1,
.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf,
.align90 = 0x61,
.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3, .g3_rx_selmuff = 0x3,
.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0, .g3_rx_selmufi = 0x3,
.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1, .g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0, .g3_rx_selmupi = 0x2,
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
}, /* Comphy2 */
{ .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
.g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
.g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1,
.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1, .g3_tx_amp_adj = 0x1,
.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0, .g3_tx_emph_en = 0x0,
.g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1,
.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf,
.align90 = 0x61,
.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3, .g3_rx_selmuff = 0x3,
.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0, .g3_rx_selmufi = 0x3,
.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1, .g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0, .g3_rx_selmupi = 0x2,
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
}, /* Comphy3 */
{ 0 }, /* Comphy4 */
{ 0 }, /* Comphy5 */
},
},
};
static const struct usb_params
usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
.polarity_invert = COMPHY_POLARITY_NO_INVERT
},
};
#endif /* __PHY_PORTING_LAYER_H */

15
plat/marvell/armada/a8k/a70x0_mochabin/mvebu_def.h Normal file
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@ -0,0 +1,15 @@
/*
* Copyright (C) 2021 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#ifndef MVEBU_DEF_H
#define MVEBU_DEF_H
#include <a8k_plat_def.h>
#define CP_COUNT 1 /* A70x0 has single CP0 */
#endif /* MVEBU_DEF_H */

20
plat/marvell/armada/a8k/a70x0_mochabin/platform.mk Normal file
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@ -0,0 +1,20 @@
#
# Copyright (C) 2021 Marvell International Ltd.
#
# SPDX-License-Identifier: BSD-3-Clause
# https://spdx.org/licenses
#
PCI_EP_SUPPORT := 0
CP_NUM := 1
$(eval $(call add_define,CP_NUM))
DOIMAGE_SEC := tools/doimage/secure/sec_img_7K.cfg
MARVELL_MOCHI_DRV := drivers/marvell/mochi/apn806_setup.c
BOARD_DIR := $(shell dirname $(lastword $(MAKEFILE_LIST)))
include plat/marvell/armada/a8k/common/a8k_common.mk
include plat/marvell/armada/common/marvell_common.mk

4
plat/marvell/armada/a8k/common/a8k_common.mk
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@ -75,6 +75,10 @@ endif
# This define specifies DDR type for BLE
$(eval $(call add_define,CONFIG_DDR4))
# This define specifies DDR topology for BLE
DDR_TOPOLOGY ?= 0
$(eval $(call add_define,DDR_TOPOLOGY))
MARVELL_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \