Merge "fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C" into integration
This commit is contained in:
Joanna Farley
TrustedFirmware Code Review
commit
0a81a42116
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, Arm Limited. All rights reserved.
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* Copyright (c) 2019-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -12,6 +12,9 @@
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/* Cortex-A76AE MIDR for revision 0 */
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#define CORTEX_A76AE_MIDR U(0x410FD0E0)
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/* Cortex-A76 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_A76AE_BHB_LOOP_COUNT U(24)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
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* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
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* Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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@ -10,7 +10,10 @@
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#include <cortex_a78.h>
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#define CORTEX_A78_AE_MIDR U(0x410FD420)
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#define CORTEX_A78_AE_MIDR U(0x410FD420)
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/* Cortex-A78AE loop count for CVE-2022-23960 mitigation */
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#define CORTEX_A78_AE_BHB_LOOP_COUNT U(32)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -10,6 +10,9 @@
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#define CORTEX_A78C_MIDR U(0x410FD4B1)
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/* Cortex-A76 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_A78C_BHB_LOOP_COUNT U(32)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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@ -1,12 +1,15 @@
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/*
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* Copyright (c) 2019, Arm Limited. All rights reserved.
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* Copyright (c) 2019-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a76ae.h>
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#include <cpu_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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@ -18,14 +21,46 @@
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#error "Cortex-A76AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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/* ---------------------------------------------
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A76AE_BHB_LOOP_COUNT, cortex_a76ae
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#endif /* WORKAROUND_CVE_2022_23960 */
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif /* WORKAROUND_CVE_2022_23960 */
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ret
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endfunc check_errata_cve_2022_23960
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/* --------------------------------------------
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* The CPU Ops reset function for Cortex-A76AE.
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* Shall clobber: x0-x19
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* --------------------------------------------
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*/
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func cortex_a76ae_reset_func
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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/*
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* The Cortex-A76ae generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_cortex_a76ae
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msr vbar_el3, x0
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isb
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#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
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ret
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endfunc cortex_a76ae_reset_func
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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* ----------------------------------------------------
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*/
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func cortex_a76ae_core_pwr_dwn
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/* ---------------------------------------------
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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* ---------------------------------------------------
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*/
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mrs x0, CORTEX_A76AE_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A76AE_CORE_PWRDN_EN_MASK
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@ -39,6 +74,18 @@ endfunc cortex_a76ae_core_pwr_dwn
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* Errata printing function for Cortex-A76AE. Must follow AAPCS.
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*/
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func cortex_a76ae_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata WORKAROUND_CVE_2022_23960, cortex_a76ae, cve_2022_23960
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a76ae_errata_report
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#endif /* REPORT_ERRATA */
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@ -62,5 +109,5 @@ func cortex_a76ae_cpu_reg_dump
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ret
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endfunc cortex_a76ae_cpu_reg_dump
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declare_cpu_ops cortex_a76ae, CORTEX_A76AE_MIDR, CPU_NO_RESET_FUNC, \
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declare_cpu_ops cortex_a76ae, CORTEX_A76AE_MIDR, cortex_a76ae_reset_func, \
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cortex_a76ae_core_pwr_dwn
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
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* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
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* Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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@ -11,12 +11,17 @@
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#include <cortex_a78_ae.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae
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#endif /* WORKAROUND_CVE_2022_23960 */
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/* --------------------------------------------------
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* Errata Workaround for A78 AE Erratum 1941500.
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* This applies to revisions r0p0 and r0p1 of A78 AE.
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@ -99,6 +104,15 @@ func check_errata_1951502
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b cpu_rev_var_range
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endfunc check_errata_1951502
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2022_23960
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A78-AE
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* -------------------------------------------------
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@ -138,8 +152,16 @@ func cortex_a78_ae_reset_func
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msr CPUAMCNTENSET1_EL0, x0
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#endif
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isb
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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/*
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* The Cortex-A78AE generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_cortex_a78_ae
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
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isb
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ret x19
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endfunc cortex_a78_ae_reset_func
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@ -175,6 +197,7 @@ func cortex_a78_ae_errata_report
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*/
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report_errata ERRATA_A78_AE_1941500, cortex_a78_ae, 1941500
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report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502
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report_errata WORKAROUND_CVE_2022_23960, cortex_a78_ae, cve_2022_23960
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ldp x8, x30, [sp], #16
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ret
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -10,12 +10,43 @@
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#include <cortex_a78c.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c
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#endif /* WORKAROUND_CVE_2022_23960 */
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2022_23960
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A78C
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* -------------------------------------------------
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*/
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func cortex_a78c_reset_func
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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/*
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* The Cortex-A78c generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_cortex_a78c
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
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isb
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ret
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endfunc cortex_a78c_reset_func
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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@ -37,6 +68,18 @@ endfunc cortex_a78c_core_pwr_dwn
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* Errata printing function for Cortex A78C. Must follow AAPCS.
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*/
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func cortex_a78c_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a78c_errata_report
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#endif
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@ -61,5 +104,5 @@ func cortex_a78c_cpu_reg_dump
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endfunc cortex_a78c_cpu_reg_dump
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declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \
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CPU_NO_RESET_FUNC, \
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cortex_a78c_reset_func, \
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cortex_a78c_core_pwr_dwn
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