Tegra: assembly version of the 'plat_core_pos_by_mpidr' handler
The 'plat_core_pos_by_mpidr' handler gets called very early during boot and the compiler generated code overwrites the caller's registers. This patch converts the 'plat_core_pos_by_mpidr' handler into an assembly function and uses registers x0-x3, to fix this anomaly. Change-Id: I8d974e007a0bad039defaf77b11a180d899ead3c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -39,6 +39,7 @@
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.globl plat_crash_console_init
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl plat_crash_console_flush
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.weak plat_core_pos_by_mpidr
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.globl tegra_secure_entrypoint
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.globl tegra_secure_entrypoint
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.globl plat_reset_handler
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.globl plat_reset_handler
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@ -270,6 +271,42 @@ _end: mov x0, x20
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ret
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ret
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endfunc plat_reset_handler
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endfunc plat_reset_handler
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/* ------------------------------------------------------
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* int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
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*
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* This function implements a part of the critical
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* interface between the psci generic layer and the
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* platform that allows the former to query the platform
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* to convert an MPIDR to a unique linear index. An error
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* code (-1) is returned in case the MPIDR is invalid.
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*
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* Clobbers: x0-x3
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* ------------------------------------------------------
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*/
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func plat_core_pos_by_mpidr
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lsr x1, x0, #MPIDR_AFF0_SHIFT
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and x1, x1, #MPIDR_AFFLVL_MASK /* core id */
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lsr x2, x0, #MPIDR_AFF1_SHIFT
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and x2, x2, #MPIDR_AFFLVL_MASK /* cluster id */
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/* core_id >= PLATFORM_MAX_CPUS_PER_CLUSTER */
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mov x0, #-1
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cmp x1, #(PLATFORM_MAX_CPUS_PER_CLUSTER - 1)
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b.gt 1f
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/* cluster_id >= PLATFORM_CLUSTER_COUNT */
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cmp x2, #(PLATFORM_CLUSTER_COUNT - 1)
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b.gt 1f
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/* CorePos = CoreId + (ClusterId * cpus per cluster) */
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mov x3, #PLATFORM_MAX_CPUS_PER_CLUSTER
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mul x3, x3, x2
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add x0, x1, x3
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1:
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ret
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endfunc plat_core_pos_by_mpidr
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/* ----------------------------------------
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/* ----------------------------------------
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* Secure entrypoint function for CPU boot
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* Secure entrypoint function for CPU boot
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* ----------------------------------------
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* ----------------------------------------
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@ -32,5 +32,4 @@ BL31_SOURCES += drivers/delay_timer/delay_timer.c \
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${COMMON_DIR}/tegra_io_storage.c \
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${COMMON_DIR}/tegra_io_storage.c \
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${COMMON_DIR}/tegra_platform.c \
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${COMMON_DIR}/tegra_platform.c \
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${COMMON_DIR}/tegra_pm.c \
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${COMMON_DIR}/tegra_pm.c \
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${COMMON_DIR}/tegra_sip_calls.c \
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${COMMON_DIR}/tegra_sip_calls.c
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${COMMON_DIR}/tegra_topology.c
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@ -1,48 +0,0 @@
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/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <arch.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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#pragma weak plat_core_pos_by_mpidr
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/*******************************************************************************
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* This function implements a part of the critical interface between the psci
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* generic layer and the platform that allows the former to query the platform
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* to convert an MPIDR to a unique linear index. An error code (-1) is returned
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* in case the MPIDR is invalid.
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******************************************************************************/
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int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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u_register_t cluster_id, cpu_id;
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int32_t result;
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cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) &
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(u_register_t)MPIDR_AFFLVL_MASK;
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cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) &
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(u_register_t)MPIDR_AFFLVL_MASK;
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/* CorePos = CoreId + (ClusterId * cpus per cluster) */
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result = (int32_t)cpu_id + ((int32_t)cluster_id *
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PLATFORM_MAX_CPUS_PER_CLUSTER);
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if (cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) {
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result = PSCI_E_NOT_PRESENT;
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}
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/*
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* Validate cpu_id by checking whether it represents a CPU in
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* one of the two clusters present on the platform.
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*/
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if (cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER) {
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result = PSCI_E_NOT_PRESENT;
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}
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return result;
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}
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