From 0b0e67669814139c6818e61e03d0d0e3314fdc99 Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Fri, 18 Feb 2022 15:27:45 +0800 Subject: [PATCH] feat(ls1088aqds): add ls1088aqds board support Add QDS support for ls1088a. Signed-off-by: Ruchika Gupta Signed-off-by: York Sun Signed-off-by: Pankaj Gupta Signed-off-by: Jiafei Pan Change-Id: I6c7a7a23fa6b9ba01c011a7e6237f8063d45e261 --- plat/nxp/soc-ls1088a/ls1088aqds/ddr_init.c | 84 +++++++++++++++++++ plat/nxp/soc-ls1088a/ls1088aqds/plat_def.h | 81 ++++++++++++++++++ plat/nxp/soc-ls1088a/ls1088aqds/platform.c | 28 +++++++ plat/nxp/soc-ls1088a/ls1088aqds/platform.mk | 31 +++++++ .../nxp/soc-ls1088a/ls1088aqds/platform_def.h | 13 +++ plat/nxp/soc-ls1088a/ls1088aqds/policy.h | 16 ++++ 6 files changed, 253 insertions(+) create mode 100644 plat/nxp/soc-ls1088a/ls1088aqds/ddr_init.c create mode 100644 plat/nxp/soc-ls1088a/ls1088aqds/plat_def.h create mode 100644 plat/nxp/soc-ls1088a/ls1088aqds/platform.c create mode 100644 plat/nxp/soc-ls1088a/ls1088aqds/platform.mk create mode 100644 plat/nxp/soc-ls1088a/ls1088aqds/platform_def.h create mode 100644 plat/nxp/soc-ls1088a/ls1088aqds/policy.h diff --git a/plat/nxp/soc-ls1088a/ls1088aqds/ddr_init.c b/plat/nxp/soc-ls1088a/ls1088aqds/ddr_init.c new file mode 100644 index 000000000..b7397ba3e --- /dev/null +++ b/plat/nxp/soc-ls1088a/ls1088aqds/ddr_init.c @@ -0,0 +1,84 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include + +#include +#include + +#ifdef CONFIG_STATIC_DDR +#error No static value defined +#endif + +static const struct rc_timing rce[] = { + {U(1600), U(8), U(8)}, + {U(1867), U(8), U(8)}, + {U(2134), U(8), U(9)}, + {} +}; + +static const struct board_timing udimm[] = { + {U(0x04), rce, U(0x01020307), U(0x08090b06)}, +}; + +int ddr_board_options(struct ddr_info *priv) +{ + int ret; + struct memctl_opt *popts = &priv->opt; + + if (popts->rdimm != 0) { + debug("RDIMM parameters not set.\n"); + return -EINVAL; + } + + ret = cal_board_params(priv, udimm, ARRAY_SIZE(udimm)); + if (ret != 0) { + return ret; + } + + popts->addr_hash = 1; + popts->cpo_sample = U(0x7b); + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | + DDR_CDR2_VREF_TRAIN_EN | + DDR_CDR2_VREF_RANGE_2; + + return 0; +} + +long long init_ddr(void) +{ + int spd_addr[] = { NXP_SPD_EEPROM0 }; + struct ddr_info info; + struct sysinfo sys; + long long dram_size; + + zeromem(&sys, sizeof(sys)); + get_clocks(&sys); + debug("platform clock %lu\n", sys.freq_platform); + debug("DDR PLL %lu\n", sys.freq_ddr_pll0); + + zeromem(&info, sizeof(struct ddr_info)); + info.num_ctlrs = NUM_OF_DDRC; + info.dimm_on_ctlr = DDRC_NUM_DIMM; + info.clk = get_ddr_freq(&sys, 0); + info.spd_addr = spd_addr; + info.ddr[0] = (void *)NXP_DDR_ADDR; + + dram_size = dram_init(&info); + if (dram_size < 0) { + ERROR("DDR init failed.\n"); + } + + erratum_a008850_post(); + + return dram_size; +} diff --git a/plat/nxp/soc-ls1088a/ls1088aqds/plat_def.h b/plat/nxp/soc-ls1088a/ls1088aqds/plat_def.h new file mode 100644 index 000000000..ebd3a2618 --- /dev/null +++ b/plat/nxp/soc-ls1088a/ls1088aqds/plat_def.h @@ -0,0 +1,81 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_DEF_H +#define PLAT_DEF_H + +#include +/* + * Required without TBBR. + * To include the defines for DDR PHY + * Images. + */ +#include + +#include +#include + +#define NXP_SPD_EEPROM0 0x51 + +#define NXP_SYSCLK_FREQ 100000000 +#define NXP_DDRCLK_FREQ 100000000 + +/* UART related definition */ +#define NXP_CONSOLE_ADDR NXP_UART_ADDR +#define NXP_CONSOLE_BAUDRATE 115200 + +/* Size of cacheable stacks */ +#if defined(IMAGE_BL2) +#if defined(TRUSTED_BOARD_BOOT) +#define PLATFORM_STACK_SIZE 0x2000 +#else +#define PLATFORM_STACK_SIZE 0x1000 +#endif +#elif defined(IMAGE_BL31) +#define PLATFORM_STACK_SIZE 0x1000 +#endif + +#define BL2_START NXP_OCRAM_ADDR +#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) +#define BL2_NOLOAD_START NXP_OCRAM_ADDR +#define BL2_NOLOAD_LIMIT BL2_BASE + +/* IO defines as needed by IO driver framework */ +#define MAX_IO_DEVICES 4 +#define MAX_IO_BLOCK_DEVICES 1 +#define MAX_IO_HANDLES 4 + +/* + * FIP image defines - Offset at which FIP Image would be present + * Image would include Bl31 , Bl33 and Bl32 (optional) + */ +#ifdef POLICY_FUSE_PROVISION +#define MAX_FIP_DEVICES 2 +#endif + +#ifndef MAX_FIP_DEVICES +#define MAX_FIP_DEVICES 1 +#endif + +#define BL32_IRQ_SEC_PHY_TIMER 29 +#define BL31_WDOG_SEC 89 + +/* + * ID of the secure physical generic timer interrupt used by the BL32. + */ +#define PLAT_LS_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) + +/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ +#define PLAT_LS_G0_IRQ_PROPS(grp) \ + INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) + + +#endif /* PLAT_DEF_H */ diff --git a/plat/nxp/soc-ls1088a/ls1088aqds/platform.c b/plat/nxp/soc-ls1088a/ls1088aqds/platform.c new file mode 100644 index 000000000..8b3eadabf --- /dev/null +++ b/plat/nxp/soc-ls1088a/ls1088aqds/platform.c @@ -0,0 +1,28 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#pragma weak board_enable_povdd +#pragma weak board_disable_povdd + +bool board_enable_povdd(void) +{ +#ifdef CONFIG_POVDD_ENABLE + return true; +#else + return false; +#endif +} + +bool board_disable_povdd(void) +{ +#ifdef CONFIG_POVDD_ENABLE + return true; +#else + return false; +#endif +} diff --git a/plat/nxp/soc-ls1088a/ls1088aqds/platform.mk b/plat/nxp/soc-ls1088a/ls1088aqds/platform.mk new file mode 100644 index 000000000..97ccf260d --- /dev/null +++ b/plat/nxp/soc-ls1088a/ls1088aqds/platform.mk @@ -0,0 +1,31 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# board-specific build parameters +BOOT_MODE ?= qspi +BOARD := ls1088aqds + +# DDR Compilation Configs +NUM_OF_DDRC := 1 +DDRC_NUM_DIMM := 1 +DDR_ECC_EN := yes + +# On-Board Flash Details +QSPI_FLASH_SZ := 0x4000000 +NOR_FLASH_SZ := 0x20000000 + +BL2_SOURCES += ${BOARD_PATH}/ddr_init.c \ + ${BOARD_PATH}/platform.c + +SUPPORTED_BOOT_MODE := qspi \ + sd \ + nor + +# Adding platform board build info +include plat/nxp/common/plat_make_helper/plat_common_def.mk + +# Adding SoC build info +include plat/nxp/soc-ls1088a/soc.mk diff --git a/plat/nxp/soc-ls1088a/ls1088aqds/platform_def.h b/plat/nxp/soc-ls1088a/ls1088aqds/platform_def.h new file mode 100644 index 000000000..7daf1c02c --- /dev/null +++ b/plat/nxp/soc-ls1088a/ls1088aqds/platform_def.h @@ -0,0 +1,13 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include +#include + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/nxp/soc-ls1088a/ls1088aqds/policy.h b/plat/nxp/soc-ls1088a/ls1088aqds/policy.h new file mode 100644 index 000000000..0eaafae5b --- /dev/null +++ b/plat/nxp/soc-ls1088a/ls1088aqds/policy.h @@ -0,0 +1,16 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef POLICY_H +#define POLICY_H + +/* + * Set this to 0x0 to leave the default SMMU page size in sACR + * Set this to 0x1 to change the SMMU page size to 64K + */ +#define POLICY_SMMU_PAGESZ_64K 0x1 + +#endif /* POLICY_H */