Merge changes from topic "zynqmp-misc-enhancement" into integration
* changes: plat: xilinx: zynqmp: Enable log messages for debug plat: zynqmp: Change macro name of PM_BOOT_HEALTH_STATUS_REG
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commit
0b18d5a5d6
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@ -104,9 +104,12 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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else if (ret != FSBL_HANDOFF_SUCCESS)
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panic();
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}
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NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
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NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
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if (bl32_image_ep_info.pc) {
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VERBOSE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
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}
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if (bl33_image_ep_info.pc) {
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VERBOSE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
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}
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}
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/* Enable the test setup */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -341,8 +341,9 @@
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#define PGGS_BASEADDR (0xFFD80050U)
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#define PGGS_NUM_REGS U(4)
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/* Warm restart boot health status register and mask */
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#define PM_BOOT_HEALTH_STATUS_REG (GGS_BASEADDR + U(0x10))
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/* PMU GGS4 register 4 is used for warm restart boot health status */
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#define PMU_GLOBAL_GEN_STORAGE4 (GGS_BASEADDR + 0x10)
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/* Warm restart boot health status mask */
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#define PM_BOOT_HEALTH_STATUS_MASK U(0x01)
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/*AFI registers */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -575,7 +575,7 @@ static enum pm_ret_status pm_ioctl_ulpi_reset(void)
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*/
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static enum pm_ret_status pm_ioctl_set_boot_health_status(unsigned int value)
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{
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return pm_mmio_write(PM_BOOT_HEALTH_STATUS_REG,
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return pm_mmio_write(PMU_GLOBAL_GEN_STORAGE4,
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PM_BOOT_HEALTH_STATUS_MASK, value);
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}
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