From 5819e23bc47c860872141caf42bddddb1b8679a5 Mon Sep 17 00:00:00 2001 From: nayanpatel-arm Date: Wed, 6 Oct 2021 15:31:24 -0700 Subject: [PATCH 1/6] fix(errata): workaround for Neoverse-N2 erratum 2242415 Neoverse-N2 erratum 2242415 is a Cat B erratum that applies to revision r0p0 of CPU. It is still open. The workaround is to set CPUACTLR_EL1[22] to 1'b1. Setting CPUACTLR_EL1[22] will cause CFP instruction to invalidate all branch predictor resources regardless of context. SDEN can be found here: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: nayanpatel-arm Change-Id: I442be81fbc32e21fed51a84f59584df17f845e96 --- docs/design/cpu-specific-build-macros.rst | 11 ++++---- include/lib/cpus/aarch64/neoverse_n2.h | 1 + lib/cpus/aarch64/neoverse_n2.S | 34 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++ 4 files changed, 49 insertions(+), 5 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index eebeaa251..b19c534cb 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -340,11 +340,6 @@ For Neoverse N1, the following errata build flags are defined : CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for revisions r0p0, r1p0, and r2p0 there is no workaround. -For Neoverse N2, the following errata build flags are defined : - -- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 - CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open. - For Neoverse V1, the following errata build flags are defined : - ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 @@ -407,6 +402,9 @@ For Cortex-A710, the following errata build flags are defined : For Neoverse N2, the following errata build flags are defined : +- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 + CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open. + - ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. @@ -422,6 +420,9 @@ For Neoverse N2, the following errata build flags are defined : - ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. +- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 + CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. + DSU Errata Workarounds ---------------------- diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h index f414cb53c..8ba62a3f7 100644 --- a/include/lib/cpus/aarch64/neoverse_n2.h +++ b/include/lib/cpus/aarch64/neoverse_n2.h @@ -28,6 +28,7 @@ ******************************************************************************/ #define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 #define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) +#define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) /******************************************************************************* * CPU Auxiliary Control register 2 specific definitions. diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index 330cc596a..c197590ba 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -183,6 +183,34 @@ func check_errata_2138956 b cpu_rev_var_ls endfunc check_errata_2138956 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2242415. + * This applies to revision r0p0 of Neoverse N2. it is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * -------------------------------------------------- + */ +func errata_n2_2242415_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2242415 + cbz x0, 1f + + /* Apply instruction patching sequence */ + mrs x1, NEOVERSE_N2_CPUACTLR_EL1 + orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 + msr NEOVERSE_N2_CPUACTLR_EL1, x1 +1: + ret x17 +endfunc errata_n2_2242415_wa + +func check_errata_2242415 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2242415 + /* -------------------------------------------------- * Errata Workaround for Neoverse N2 Erratum 2138953. * This applies to revision r0p0 of Neoverse N2. it is still open. @@ -258,6 +286,11 @@ func neoverse_n2_reset_func bl errata_n2_2138953_wa #endif +#if ERRATA_N2_2242415 + mov x0, x18 + bl errata_n2_2242415_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, cptr_el3 @@ -324,6 +357,7 @@ func neoverse_n2_errata_report report_errata ERRATA_N2_2189731, neoverse_n2, 2189731 report_errata ERRATA_N2_2138956, neoverse_n2, 2138956 report_errata ERRATA_N2_2138953, neoverse_n2, 2138953 + report_errata ERRATA_N2_2242415, neoverse_n2, 2242415 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 138f7a572..4224fcc65 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -461,6 +461,10 @@ ERRATA_N2_2138956 ?=0 # to revision r0p0 of the Neoverse N2 cpu and is still open. ERRATA_N2_2138953 ?=0 +# Flag to apply erratum 2242415 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu and is still open. +ERRATA_N2_2242415 ?=0 + # Flag to apply erratum 2055002 workaround during reset. This erratum applies # to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open. ERRATA_A710_2055002 ?=0 @@ -862,6 +866,10 @@ $(eval $(call add_define,ERRATA_N2_2138956)) $(eval $(call assert_boolean,ERRATA_N2_2138953)) $(eval $(call add_define,ERRATA_N2_2138953)) +# Process ERRATA_N2_2242415 flag +$(eval $(call assert_boolean,ERRATA_N2_2242415)) +$(eval $(call add_define,ERRATA_N2_2242415)) + # Process ERRATA_A710_2055002 flag $(eval $(call assert_boolean,ERRATA_A710_2055002)) $(eval $(call add_define,ERRATA_A710_2055002)) From c948185c973c13df36c62c4bcb50e22b14d6e06a Mon Sep 17 00:00:00 2001 From: nayanpatel-arm Date: Wed, 20 Oct 2021 18:28:58 -0700 Subject: [PATCH 2/6] fix(errata): workaround for Neoverse-N2 erratum 2138958 Neoverse-N2 erratum 2138958 is a Cat B erratum that applies to revision r0p0 of CPU. It is still open. The workaround is to set CPUACTLR5_EL1[13] to 1'b1. SDEN can be found here: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: nayanpatel-arm Change-Id: I5247f8f8eef08d38c169aad6d2c5501ac387c720 --- docs/design/cpu-specific-build-macros.rst | 3 ++ include/lib/cpus/aarch64/neoverse_n2.h | 1 + lib/cpus/aarch64/neoverse_n2.S | 34 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++ 4 files changed, 46 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index b19c534cb..cd4d0fdca 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -423,6 +423,9 @@ For Neoverse N2, the following errata build flags are defined : - ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. +- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 + CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. + DSU Errata Workarounds ---------------------- diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h index 8ba62a3f7..a457f2a54 100644 --- a/include/lib/cpus/aarch64/neoverse_n2.h +++ b/include/lib/cpus/aarch64/neoverse_n2.h @@ -41,6 +41,7 @@ ******************************************************************************/ #define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) /******************************************************************************* * CPU Auxiliary Control register specific definitions. diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index c197590ba..ff569fb23 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -240,6 +240,34 @@ func check_errata_2138953 b cpu_rev_var_ls endfunc check_errata_2138953 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2138958. + * This applies to revision r0p0 of Neoverse N2. it is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * -------------------------------------------------- + */ +func errata_n2_2138958_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2138958 + cbz x0, 1f + + /* Apply instruction patching sequence */ + mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 + orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 + msr NEOVERSE_N2_CPUACTLR5_EL1, x1 +1: + ret x17 +endfunc errata_n2_2138958_wa + +func check_errata_2138958 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2138958 + /* ------------------------------------------- * The CPU Ops reset function for Neoverse N2. * ------------------------------------------- @@ -291,6 +319,11 @@ func neoverse_n2_reset_func bl errata_n2_2242415_wa #endif +#if ERRATA_N2_2138958 + mov x0, x18 + bl errata_n2_2138958_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, cptr_el3 @@ -358,6 +391,7 @@ func neoverse_n2_errata_report report_errata ERRATA_N2_2138956, neoverse_n2, 2138956 report_errata ERRATA_N2_2138953, neoverse_n2, 2138953 report_errata ERRATA_N2_2242415, neoverse_n2, 2242415 + report_errata ERRATA_N2_2138958, neoverse_n2, 2138958 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 4224fcc65..b676987d7 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -465,6 +465,10 @@ ERRATA_N2_2138953 ?=0 # to revision r0p0 of the Neoverse N2 cpu and is still open. ERRATA_N2_2242415 ?=0 +# Flag to apply erratum 2138958 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu and is still open. +ERRATA_N2_2138958 ?=0 + # Flag to apply erratum 2055002 workaround during reset. This erratum applies # to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open. ERRATA_A710_2055002 ?=0 @@ -870,6 +874,10 @@ $(eval $(call add_define,ERRATA_N2_2138953)) $(eval $(call assert_boolean,ERRATA_N2_2242415)) $(eval $(call add_define,ERRATA_N2_2242415)) +# Process ERRATA_N2_2138958 flag +$(eval $(call assert_boolean,ERRATA_N2_2138958)) +$(eval $(call add_define,ERRATA_N2_2138958)) + # Process ERRATA_A710_2055002 flag $(eval $(call assert_boolean,ERRATA_A710_2055002)) $(eval $(call add_define,ERRATA_A710_2055002)) From 603806d1376c4b18211fb1d4cc338153de026c32 Mon Sep 17 00:00:00 2001 From: nayanpatel-arm Date: Thu, 7 Oct 2021 17:59:33 -0700 Subject: [PATCH 3/6] fix(errata): workaround for Neoverse-N2 erratum 2242400 Neoverse-N2 erratum 2242400 is a Cat B erratum that applies to revision r0p0 of CPU. It is still open. The workaround is to set CPUACTLR5_EL1[17] to 1'b1 followed by setting few system control registers to specific values as per attached SDEN document. SDEN can be found here: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: nayanpatel-arm Change-Id: I6a9cb4a23238b8b511802a1ee9fcc5b207137649 --- docs/design/cpu-specific-build-macros.rst | 3 ++ include/lib/cpus/aarch64/neoverse_n2.h | 1 + lib/cpus/aarch64/neoverse_n2.S | 51 +++++++++++++++++++++-- lib/cpus/cpu-ops.mk | 8 ++++ 4 files changed, 59 insertions(+), 4 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index cd4d0fdca..74be11bc6 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -426,6 +426,9 @@ For Neoverse N2, the following errata build flags are defined : - ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. +- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 + CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. + DSU Errata Workarounds ---------------------- diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h index a457f2a54..a1e676ec2 100644 --- a/include/lib/cpus/aarch64/neoverse_n2.h +++ b/include/lib/cpus/aarch64/neoverse_n2.h @@ -42,6 +42,7 @@ #define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) /******************************************************************************* * CPU Auxiliary Control register specific definitions. diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index ff569fb23..869aa41e1 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -268,6 +268,43 @@ func check_errata_2138958 b cpu_rev_var_ls endfunc check_errata_2138958 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2242400. + * This applies to revision r0p0 of Neoverse N2. it is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * -------------------------------------------------- + */ +func errata_n2_2242400_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2242400 + cbz x0, 1f + + /* Apply instruction patching sequence */ + mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 + orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 + msr NEOVERSE_N2_CPUACTLR5_EL1, x1 + ldr x0, =0x2 + msr S3_6_c15_c8_0, x0 + ldr x0, =0x10F600E000 + msr S3_6_c15_c8_2, x0 + ldr x0, =0x10FF80E000 + msr S3_6_c15_c8_3, x0 + ldr x0, =0x80000000003FF + msr S3_6_c15_c8_1, x0 + isb +1: + ret x17 +endfunc errata_n2_2242400_wa + +func check_errata_2242400 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2242400 + /* ------------------------------------------- * The CPU Ops reset function for Neoverse N2. * ------------------------------------------- @@ -294,13 +331,13 @@ func neoverse_n2_reset_func #endif #if ERRATA_N2_2025414 - mov x0, x18 - bl errata_n2_2025414_wa + mov x0, x18 + bl errata_n2_2025414_wa #endif #if ERRATA_N2_2189731 - mov x0, x18 - bl errata_n2_2189731_wa + mov x0, x18 + bl errata_n2_2189731_wa #endif @@ -324,6 +361,11 @@ func neoverse_n2_reset_func bl errata_n2_2138958_wa #endif +#if ERRATA_N2_2242400 + mov x0, x18 + bl errata_n2_2242400_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, cptr_el3 @@ -392,6 +434,7 @@ func neoverse_n2_errata_report report_errata ERRATA_N2_2138953, neoverse_n2, 2138953 report_errata ERRATA_N2_2242415, neoverse_n2, 2242415 report_errata ERRATA_N2_2138958, neoverse_n2, 2138958 + report_errata ERRATA_N2_2242400, neoverse_n2, 2242400 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index b676987d7..f0da13919 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -469,6 +469,10 @@ ERRATA_N2_2242415 ?=0 # to revision r0p0 of the Neoverse N2 cpu and is still open. ERRATA_N2_2138958 ?=0 +# Flag to apply erratum 2242400 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu and is still open. +ERRATA_N2_2242400 ?=0 + # Flag to apply erratum 2055002 workaround during reset. This erratum applies # to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open. ERRATA_A710_2055002 ?=0 @@ -878,6 +882,10 @@ $(eval $(call add_define,ERRATA_N2_2242415)) $(eval $(call assert_boolean,ERRATA_N2_2138958)) $(eval $(call add_define,ERRATA_N2_2138958)) +# Process ERRATA_N2_2242400 flag +$(eval $(call assert_boolean,ERRATA_N2_2242400)) +$(eval $(call add_define,ERRATA_N2_2242400)) + # Process ERRATA_A710_2055002 flag $(eval $(call assert_boolean,ERRATA_A710_2055002)) $(eval $(call add_define,ERRATA_A710_2055002)) From 0d2d99924e1be548e75c46cfd536f7503cf863e0 Mon Sep 17 00:00:00 2001 From: nayanpatel-arm Date: Wed, 20 Oct 2021 17:30:46 -0700 Subject: [PATCH 4/6] fix(errata): workaround for Neoverse-N2 erratum 2280757 Neoverse-N2 erratum 2280757 is a Cat B erratum that applies to revision r0p0 of CPU. It is still open. The workaround is to set CPUACTLR_EL1[22] to 1'b1. Setting CPUACTLR_EL1[22] will cause CFP instruction to invalidate all branch predictor resources regardless of context. SDEN can be found here: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: nayanpatel-arm Change-Id: I615bcc1f993c45659b8b6f1a34fca0eb490f8add --- docs/design/cpu-specific-build-macros.rst | 3 ++ lib/cpus/aarch64/neoverse_n2.S | 34 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++ 3 files changed, 45 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 74be11bc6..b5ec36318 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -429,6 +429,9 @@ For Neoverse N2, the following errata build flags are defined : - ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. +- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 + CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. + DSU Errata Workarounds ---------------------- diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index 869aa41e1..621aded7c 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -305,6 +305,34 @@ func check_errata_2242400 b cpu_rev_var_ls endfunc check_errata_2242400 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2280757. + * This applies to revision r0p0 of Neoverse N2. it is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * -------------------------------------------------- + */ +func errata_n2_2280757_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2280757 + cbz x0, 1f + + /* Apply instruction patching sequence */ + mrs x1, NEOVERSE_N2_CPUACTLR_EL1 + orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 + msr NEOVERSE_N2_CPUACTLR_EL1, x1 +1: + ret x17 +endfunc errata_n2_2280757_wa + +func check_errata_2280757 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2280757 + /* ------------------------------------------- * The CPU Ops reset function for Neoverse N2. * ------------------------------------------- @@ -366,6 +394,11 @@ func neoverse_n2_reset_func bl errata_n2_2242400_wa #endif +#if ERRATA_N2_2280757 + mov x0, x18 + bl errata_n2_2280757_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, cptr_el3 @@ -435,6 +468,7 @@ func neoverse_n2_errata_report report_errata ERRATA_N2_2242415, neoverse_n2, 2242415 report_errata ERRATA_N2_2138958, neoverse_n2, 2138958 report_errata ERRATA_N2_2242400, neoverse_n2, 2242400 + report_errata ERRATA_N2_2280757, neoverse_n2, 2280757 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index f0da13919..cdb978b09 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -473,6 +473,10 @@ ERRATA_N2_2138958 ?=0 # to revision r0p0 of the Neoverse N2 cpu and is still open. ERRATA_N2_2242400 ?=0 +# Flag to apply erratum 2280757 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu and is still open. +ERRATA_N2_2280757 ?=0 + # Flag to apply erratum 2055002 workaround during reset. This erratum applies # to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open. ERRATA_A710_2055002 ?=0 @@ -886,6 +890,10 @@ $(eval $(call add_define,ERRATA_N2_2138958)) $(eval $(call assert_boolean,ERRATA_N2_2242400)) $(eval $(call add_define,ERRATA_N2_2242400)) +# Process ERRATA_N2_2280757 flag +$(eval $(call assert_boolean,ERRATA_N2_2280757)) +$(eval $(call add_define,ERRATA_N2_2280757)) + # Process ERRATA_A710_2055002 flag $(eval $(call assert_boolean,ERRATA_A710_2055002)) $(eval $(call add_define,ERRATA_A710_2055002)) From 1ea9190c6a4d2299c6dc19adc0bbe93d4f051eff Mon Sep 17 00:00:00 2001 From: johpow01 Date: Thu, 2 Sep 2021 17:53:30 -0500 Subject: [PATCH 5/6] fix(errata): workaround for Cortex A78 erratum 2242635 Cortex A78 erratum 2242635 is a Cat B erratum present in the A78 Core. It applies to revisions r1p0, r1p1, r1p2, and is still open. The issue is also present in r0p0 but there is no workaround for this revision. SDEN can be found here: https://developer.arm.com/documentation/SDEN1401784 Signed-off-by: John Powell Change-Id: Ieca024254cabbc683ff13a70f3aeb8f2f3c5ce07 --- docs/design/cpu-specific-build-macros.rst | 4 ++ lib/cpus/aarch64/cortex_a78.S | 42 +++++++++++++++++++ lib/cpus/cpu-ops.mk | 49 ++++++++++++++--------- 3 files changed, 75 insertions(+), 20 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index b5ec36318..1d4f67ab7 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -288,6 +288,10 @@ For Cortex-A78, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It is still open. +- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 + CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue + is present in r0p0 but there is no workaround. It is still open. + For Cortex-A78 AE, the following errata build flags are defined : - ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to Cortex-A78 diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S index 4e8a228ed..a1288bab1 100644 --- a/lib/cpus/aarch64/cortex_a78.S +++ b/lib/cpus/aarch64/cortex_a78.S @@ -227,6 +227,42 @@ func check_errata_2132060 b cpu_rev_var_ls endfunc check_errata_2132060 +/* -------------------------------------------------------------------- + * Errata Workaround for A78 Erratum 2242635. + * This applies to revisions r1p0, r1p1, and r1p2 of the Cortex A78 + * processor and is still open. + * The issue also exists in r0p0 but there is no fix in that revision. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------------------------- + */ +func errata_a78_2242635_wa + /* Compare x0 against revisions r1p0 - r1p2 */ + mov x17, x30 + bl check_errata_2242635 + cbz x0, 1f + + ldr x0, =0x5 + msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ + ldr x0, =0x10F600E000 + msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ + ldr x0, =0x10FF80E000 + msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ + ldr x0, =0x80000000003FF + msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ + + isb +1: + ret x17 +endfunc errata_a78_2242635_wa + +func check_errata_2242635 + /* Applies to revisions r1p0 through r1p2. */ + mov x1, #CPU_REV(1, 0) + mov x2, #CPU_REV(1, 2) + b cpu_rev_var_range +endfunc check_errata_2242635 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A78 * ------------------------------------------------- @@ -266,6 +302,11 @@ func cortex_a78_reset_func bl errata_a78_2132060_wa #endif +#if ERRATA_A78_2242635 + mov x0, x18 + bl errata_a78_2242635_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 @@ -326,6 +367,7 @@ func cortex_a78_errata_report report_errata ERRATA_A78_1821534, cortex_a78, 1821534 report_errata ERRATA_A78_1952683, cortex_a78, 1952683 report_errata ERRATA_A78_2132060, cortex_a78, 2132060 + report_errata ERRATA_A78_2242635, cortex_a78, 2242635 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index cdb978b09..6a514ef77 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -311,6 +311,23 @@ ERRATA_A78_1941498 ?=0 # well but there is no workaround for that revision. ERRATA_A78_1951500 ?=0 +# Flag to apply erratum 1821534 workaround during reset. This erratum applies +# to revisions r0p0 and r1p0 of the A78 cpu. +ERRATA_A78_1821534 ?=0 + +# Flag to apply erratum 1952683 workaround during reset. This erratum applies +# to revision r0p0 of the A78 cpu and was fixed in the revision r1p0. +ERRATA_A78_1952683 ?=0 + +# Flag to apply erratum 2132060 workaround during reset. This erratum applies +# to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open. +ERRATA_A78_2132060 ?=0 + +# Flag to apply erratum 2242635 workaround during reset. This erratum applies +# to revisions r1p0, r1p1, and r1p2 of the A78 cpu and is open. The issue is +# present in r0p0 as well but there is no workaround for that revision. +ERRATA_A78_2242635 ?=0 + # Flag to apply erratum 1941500 workaround during reset. This erratum applies # to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open. ERRATA_A78_AE_1941500 ?=0 @@ -319,18 +336,6 @@ ERRATA_A78_AE_1941500 ?=0 # to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open. ERRATA_A78_AE_1951502 ?=0 -# Flag to apply erratum 1821534 workaround during reset. This erratum applies -# to revisions r0p0 and r1p0 of the A78 cpu. -ERRATA_A78_1821534 ?=0 - -# Flag to apply erratum 1952683 workaround during reset. This erratum applies -# to revision r0p0 of the A78 cpu and was fixed in the revision r1p0. -ERRATA_A78_1952683 ?=0 - -# Flag to apply erratum 2132060 workaround during reset. This erratum applies -# to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open. -ERRATA_A78_2132060 ?=0 - # Flag to apply T32 CLREX workaround during reset. This erratum applies # only to r0p0 and r1p0 of the Neoverse N1 cpu. ERRATA_N1_1043202 ?=0 @@ -730,14 +735,6 @@ $(eval $(call add_define,ERRATA_A78_1941498)) $(eval $(call assert_boolean,ERRATA_A78_1951500)) $(eval $(call add_define,ERRATA_A78_1951500)) -# Process ERRATA_A78_AE_1941500 flag -$(eval $(call assert_boolean,ERRATA_A78_AE_1941500)) -$(eval $(call add_define,ERRATA_A78_AE_1941500)) - -# Process ERRATA_A78_AE_1951502 flag -$(eval $(call assert_boolean,ERRATA_A78_AE_1951502)) -$(eval $(call add_define,ERRATA_A78_AE_1951502)) - # Process ERRATA_A78_1821534 flag $(eval $(call assert_boolean,ERRATA_A78_1821534)) $(eval $(call add_define,ERRATA_A78_1821534)) @@ -750,6 +747,18 @@ $(eval $(call add_define,ERRATA_A78_1952683)) $(eval $(call assert_boolean,ERRATA_A78_2132060)) $(eval $(call add_define,ERRATA_A78_2132060)) +# Process ERRATA_A78_2242635 flag +$(eval $(call assert_boolean,ERRATA_A78_2242635)) +$(eval $(call add_define,ERRATA_A78_2242635)) + +# Process ERRATA_A78_AE_1941500 flag +$(eval $(call assert_boolean,ERRATA_A78_AE_1941500)) +$(eval $(call add_define,ERRATA_A78_AE_1941500)) + +# Process ERRATA_A78_AE_1951502 flag +$(eval $(call assert_boolean,ERRATA_A78_AE_1951502)) +$(eval $(call add_define,ERRATA_A78_AE_1951502)) + # Process ERRATA_N1_1043202 flag $(eval $(call assert_boolean,ERRATA_N1_1043202)) $(eval $(call add_define,ERRATA_N1_1043202)) From 4c8fe6b17fa994a630b2a30f8666df103f2e370d Mon Sep 17 00:00:00 2001 From: johpow01 Date: Thu, 2 Sep 2021 18:29:17 -0500 Subject: [PATCH 6/6] fix(errata): workaround for Neoverse V1 erratum 2216392 Neoverse V1 erratum 2216392 is a Cat B erratum present in the V1 core. It applies to revisions r1p0 and r1p1 and is still open. The issue is also present in r0p0 but there is no workaround in that revision. SDEN can be found here: https://developer.arm.com/documentation/SDEN1401781 Signed-off-by: John Powell Change-Id: Ic2f90d79c75e8ffef01aac81eddf1bfd8b7164ab --- docs/design/cpu-specific-build-macros.rst | 5 +++ lib/cpus/aarch64/neoverse_v1.S | 43 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 9 +++++ 3 files changed, 57 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 1d4f67ab7..9d0dd5e2f 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -378,6 +378,11 @@ For Neoverse V1, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. It is still open. +- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1 + CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the + issue is present in r0p0 as well but there is no workaround for that + revision. It is still open. + For Cortex-A710, the following errata build flags are defined : - ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index 200f67de3..62a7a30cd 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -288,6 +288,43 @@ func check_errata_2108267 b cpu_rev_var_ls endfunc check_errata_2108267 + /* -------------------------------------------------- + * Errata Workaround for Neoverse V1 Errata #2216392. + * This applies to revisions r1p0 and r1p1 and is + * still open. + * This issue is also present in r0p0 but there is no + * workaround in that revision. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_neoverse_v1_2216392_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_2216392 + cbz x0, 1f + + ldr x0, =0x5 + msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ + ldr x0, =0x10F600E000 + msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ + ldr x0, =0x10FF80E000 + msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ + ldr x0, =0x80000000003FF + msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ + + isb +1: + ret x17 +endfunc errata_neoverse_v1_2216392_wa + +func check_errata_2216392 + /* Applies to revisions r1p0 and r1p1. */ + mov x1, #CPU_REV(1, 0) + mov x2, #CPU_REV(1, 1) + b cpu_rev_var_range +endfunc check_errata_2216392 + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- @@ -326,6 +363,7 @@ func neoverse_v1_errata_report report_errata ERRATA_V1_1966096, neoverse_v1, 1966096 report_errata ERRATA_V1_2139242, neoverse_v1, 2139242 report_errata ERRATA_V1_2108267, neoverse_v1, 2108267 + report_errata ERRATA_V1_2216392, neoverse_v1, 2216392 ldp x8, x30, [sp], #16 ret @@ -379,6 +417,11 @@ func neoverse_v1_reset_func bl errata_neoverse_v1_2108267_wa #endif +#if ERRATA_V1_2216392 + mov x0, x18 + bl errata_neoverse_v1_2216392_wa +#endif + ret x19 endfunc neoverse_v1_reset_func diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 6a514ef77..a5b8aae29 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -430,6 +430,11 @@ ERRATA_V1_2139242 ?=0 # to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open. ERRATA_V1_2108267 ?=0 +# Flag to apply erratum 2216392 workaround during reset. This erratum applies +# to revisions r1p0 and r1p1 of the Neoverse V1 cpu and is still open. This +# issue exists in r0p0 as well but there is no workaround for that revision. +ERRATA_V1_2216392 ?=0 + # Flag to apply erratum 1987031 workaround during reset. This erratum applies # to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. ERRATA_A710_1987031 ?=0 @@ -851,6 +856,10 @@ $(eval $(call add_define,ERRATA_V1_2139242)) $(eval $(call assert_boolean,ERRATA_V1_2108267)) $(eval $(call add_define,ERRATA_V1_2108267)) +# Process ERRATA_V1_2216392 flag +$(eval $(call assert_boolean,ERRATA_V1_2216392)) +$(eval $(call add_define,ERRATA_V1_2216392)) + # Process ERRATA_A710_1987031 flag $(eval $(call assert_boolean,ERRATA_A710_1987031)) $(eval $(call add_define,ERRATA_A710_1987031))