Tegra: memctrl_v1: disable AHB redirection after cold boot
During boot, USB3 and flash media (SDMMC/SATA) devices need access to IRAM. Because these clients connect to the MC and do not have a direct path to the IRAM, the MC implements AHB redirection during boot to allow path to IRAM. In this mode, accesses to a programmed memory address aperture are directed to the AHB bus, allowing access to the IRAM. The AHB aperture is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are initialized to disable this aperture. Once bootup is complete, we must program IRAM base/top, thus disabling access to IRAM. This patch provides functionality to disable this access. The tegra port calls this new function before jumping to the non-secure world during cold boot. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
parent
cd3de4326b
commit
0c2276e35f
|
@ -218,3 +218,29 @@ done:
|
|||
video_mem_base = phys_base;
|
||||
video_mem_size = size_in_bytes >> 20;
|
||||
}
|
||||
|
||||
/*
|
||||
* During boot, USB3 and flash media (SDMMC/SATA) devices need access to
|
||||
* IRAM. Because these clients connect to the MC and do not have a direct
|
||||
* path to the IRAM, the MC implements AHB redirection during boot to allow
|
||||
* path to IRAM. In this mode, accesses to a programmed memory address aperture
|
||||
* are directed to the AHB bus, allowing access to the IRAM. The AHB aperture
|
||||
* is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are
|
||||
* initialized to disable this aperture.
|
||||
*
|
||||
* Once bootup is complete, we must program IRAM base to 0xffffffff and
|
||||
* IRAM top to 0x00000000, thus disabling access to IRAM. DRAM is then
|
||||
* potentially accessible in this address range. These aperture registers
|
||||
* also have an access_control/lock bit. After disabling the aperture, the
|
||||
* access_control register should be programmed to lock the registers.
|
||||
*/
|
||||
void tegra_memctrl_disable_ahb_redirection(void)
|
||||
{
|
||||
/* program the aperture registers */
|
||||
tegra_mc_write_32(MC_IRAM_BASE_LO, 0xFFFFFFFF);
|
||||
tegra_mc_write_32(MC_IRAM_TOP_LO, 0);
|
||||
tegra_mc_write_32(MC_IRAM_BASE_TOP_HI, 0);
|
||||
|
||||
/* lock the aperture registers */
|
||||
tegra_mc_write_32(MC_IRAM_REG_CTRL, MC_DISABLE_IRAM_CFG_WRITES);
|
||||
}
|
||||
|
|
|
@ -581,3 +581,11 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
|
|||
*/
|
||||
mce_update_gsc_videomem();
|
||||
}
|
||||
|
||||
/*
|
||||
* This feature exists only for v1 of the Tegra Memory Controller.
|
||||
*/
|
||||
void tegra_memctrl_disable_ahb_redirection(void)
|
||||
{
|
||||
; /* do nothing */
|
||||
}
|
||||
|
|
|
@ -299,7 +299,16 @@ void bl31_platform_setup(void)
|
|||
******************************************************************************/
|
||||
void bl31_plat_runtime_setup(void)
|
||||
{
|
||||
; /* do nothing */
|
||||
/*
|
||||
* During boot, USB3 and flash media (SDMMC/SATA) devices need
|
||||
* access to IRAM. Because these clients connect to the MC and
|
||||
* do not have a direct path to the IRAM, the MC implements AHB
|
||||
* redirection during boot to allow path to IRAM. In this mode
|
||||
* accesses to a programmed memory address aperture are directed
|
||||
* to the AHB bus, allowing access to the IRAM. This mode must be
|
||||
* disabled before we jump to the non-secure world.
|
||||
*/
|
||||
tegra_memctrl_disable_ahb_redirection();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
@ -36,5 +36,6 @@ void tegra_memctrl_restore_settings(void);
|
|||
void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes);
|
||||
void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes);
|
||||
void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes);
|
||||
void tegra_memctrl_disable_ahb_redirection(void);
|
||||
|
||||
#endif /* __MEMCTRL_H__ */
|
||||
|
|
|
@ -60,6 +60,13 @@
|
|||
#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98
|
||||
#define MC_SMMU_TRANSLATION_ENABLE (~0)
|
||||
|
||||
/* MC IRAM aperture registers */
|
||||
#define MC_IRAM_BASE_LO 0x65CU
|
||||
#define MC_IRAM_TOP_LO 0x660U
|
||||
#define MC_IRAM_BASE_TOP_HI 0x980U
|
||||
#define MC_IRAM_REG_CTRL 0x964U
|
||||
#define MC_DISABLE_IRAM_CFG_WRITES 1U
|
||||
|
||||
static inline uint32_t tegra_mc_read_32(uint32_t off)
|
||||
{
|
||||
return mmio_read_32(TEGRA_MC_BASE + off);
|
||||
|
|
Loading…
Reference in New Issue