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Tegra: define MAX_XLAT_TABLES and MAX_MMAP_REGIONS per-platform 

This patch moves these address translation helper macros to individual
Tegra SoC makefiles to provide more control.

Change-Id: Ieab53c457c73747bd0deb250459befb5b7b9363f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2015-09-09 11:29:24 +05:30
parent f9b895ad25
commit 0c2a7c38f3
3 changed files with 12 additions and 2 deletions
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2
plat/nvidia/tegra/include/platform_def.h
View File

@ -84,8 +84,6 @@
* Platform specific page table and MMU setup constants
******************************************************************************/
#define ADDR_SPACE_SIZE (1ull << 32)
#define MAX_XLAT_TABLES 3
#define MAX_MMAP_REGIONS 8
/*******************************************************************************
* Some data must be aligned on the biggest cache line size in the platform.

6
plat/nvidia/tegra/soc/t132/platform_t132.mk
View File

@ -40,6 +40,12 @@ $(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
PLATFORM_MAX_CPUS_PER_CLUSTER := 2
$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
MAX_XLAT_TABLES := 3
$(eval $(call add_define,MAX_XLAT_TABLES))
MAX_MMAP_REGIONS := 8
$(eval $(call add_define,MAX_MMAP_REGIONS))
BL31_SOURCES += lib/cpus/aarch64/denver.S \
${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
${SOC_DIR}/plat_psci_handlers.c \

6
plat/nvidia/tegra/soc/t210/platform_t210.mk
View File

@ -52,6 +52,12 @@ $(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
PLATFORM_MAX_CPUS_PER_CLUSTER := 4
$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
MAX_XLAT_TABLES := 3
$(eval $(call add_define,MAX_XLAT_TABLES))
MAX_MMAP_REGIONS := 8
$(eval $(call add_define,MAX_MMAP_REGIONS))
BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
${COMMON_DIR}/drivers/flowctrl/flowctrl.c \