Tegra: define MAX_XLAT_TABLES and MAX_MMAP_REGIONS per-platform
This patch moves these address translation helper macros to individual Tegra SoC makefiles to provide more control. Change-Id: Ieab53c457c73747bd0deb250459befb5b7b9363f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -84,8 +84,6 @@
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define ADDR_SPACE_SIZE (1ull << 32)
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#define MAX_XLAT_TABLES 3
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#define MAX_MMAP_REGIONS 8
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/*******************************************************************************
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* Some data must be aligned on the biggest cache line size in the platform.
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@ -40,6 +40,12 @@ $(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
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PLATFORM_MAX_CPUS_PER_CLUSTER := 2
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$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
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MAX_XLAT_TABLES := 3
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$(eval $(call add_define,MAX_XLAT_TABLES))
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MAX_MMAP_REGIONS := 8
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$(eval $(call add_define,MAX_MMAP_REGIONS))
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BL31_SOURCES += lib/cpus/aarch64/denver.S \
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${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
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${SOC_DIR}/plat_psci_handlers.c \
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@ -52,6 +52,12 @@ $(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
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PLATFORM_MAX_CPUS_PER_CLUSTER := 4
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$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
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MAX_XLAT_TABLES := 3
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$(eval $(call add_define,MAX_XLAT_TABLES))
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MAX_MMAP_REGIONS := 8
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$(eval $(call add_define,MAX_MMAP_REGIONS))
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BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a57.S \
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${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
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