Merge pull request #957 from hzhuang1/finish_hikey_psci
Finish hikey psci
This commit is contained in:
commit
0ceb3e1e8d
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@ -4,6 +4,7 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <arm_gic.h>
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#include <assert.h>
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#include <bl_common.h>
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@ -88,6 +89,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
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/* Initialize CCI driver */
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cci_init(CCI400_BASE, cci_map, ARRAY_SIZE(cci_map));
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
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/*
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* Copy BL3-2 and BL3-3 entry point information.
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@ -15,21 +15,19 @@
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#include <hisi_sram_map.h>
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#include <mmio.h>
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#include <psci.h>
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#include <sp804_delay_timer.h>
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#include "hikey_def.h"
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#define HIKEY_CLUSTER_STATE_ON 0
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#define HIKEY_CLUSTER_STATE_OFF 1
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#define CORE_PWR_STATE(state) \
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((state)->pwr_domain_state[MPIDR_AFFLVL0])
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#define CLUSTER_PWR_STATE(state) \
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((state)->pwr_domain_state[MPIDR_AFFLVL1])
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#define SYSTEM_PWR_STATE(state) \
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((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
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static uintptr_t hikey_sec_entrypoint;
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/* There're two clusters in HiKey. */
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static int hikey_cluster_state[] = {HIKEY_CLUSTER_STATE_OFF,
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HIKEY_CLUSTER_STATE_OFF};
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/*******************************************************************************
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* Handler called when a power domain is about to be turned on. The
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* level and mpidr determine the affinity instance.
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******************************************************************************/
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static int hikey_pwr_domain_on(u_register_t mpidr)
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{
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int cpu, cluster;
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@ -54,14 +52,14 @@ static void hikey_pwr_domain_on_finish(const psci_power_state_t *target_state)
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mpidr = read_mpidr();
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cluster = MPIDR_AFFLVL1_VAL(mpidr);
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cpu = MPIDR_AFFLVL0_VAL(mpidr);
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if (hikey_cluster_state[cluster] == HIKEY_CLUSTER_STATE_OFF) {
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/*
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* Enable CCI coherency for this cluster.
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* No need for locks as no other cpu is active at the moment.
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*/
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/*
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* Enable CCI coherency for this cluster.
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* No need for locks as no other cpu is active at the moment.
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*/
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if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
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hikey_cluster_state[cluster] = HIKEY_CLUSTER_STATE_ON;
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}
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/* Zero the jump address in the mailbox for this cpu */
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hisi_pwrc_set_core_bx_addr(cpu, cluster, 0);
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@ -72,35 +70,133 @@ static void hikey_pwr_domain_on_finish(const psci_power_state_t *target_state)
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gicv2_cpuif_enable();
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}
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/*******************************************************************************
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* Handler called when a power domain is about to be turned off. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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void hikey_pwr_domain_off(const psci_power_state_t *target_state)
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{
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unsigned long mpidr;
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int cpu, cluster;
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gicv2_cpuif_disable();
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mpidr = read_mpidr();
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cluster = MPIDR_AFFLVL1_VAL(mpidr);
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cpu = MPIDR_AFFLVL0_VAL(mpidr);
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if (target_state->pwr_domain_state[MPIDR_AFFLVL1] ==
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PLAT_MAX_OFF_STATE) {
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gicv2_cpuif_disable();
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hisi_ipc_cpu_off(cpu, cluster);
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if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE);
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cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
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hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE);
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hisi_ipc_cluster_off(cpu, cluster);
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hikey_cluster_state[cluster] = HIKEY_CLUSTER_STATE_OFF;
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}
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hisi_ipc_cpu_off(cpu, cluster);
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}
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/*******************************************************************************
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* Handler to reboot the system.
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******************************************************************************/
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static void hikey_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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u_register_t mpidr = read_mpidr_el1();
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unsigned int cpu = mpidr & MPIDR_CPU_MASK;
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unsigned int cluster =
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(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS;
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if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
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return;
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if (CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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/* Program the jump address for the target cpu */
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hisi_pwrc_set_core_bx_addr(cpu, cluster, hikey_sec_entrypoint);
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gicv2_cpuif_disable();
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if (SYSTEM_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
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hisi_ipc_cpu_suspend(cpu, cluster);
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}
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/* Perform the common cluster specific operations */
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if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE);
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cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
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hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE);
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if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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hisi_pwrc_set_cluster_wfi(1);
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hisi_pwrc_set_cluster_wfi(0);
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hisi_ipc_psci_system_off();
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} else
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hisi_ipc_cluster_suspend(cpu, cluster);
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}
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}
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static void hikey_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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unsigned long mpidr;
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unsigned int cluster, cpu;
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/* Nothing to be done on waking up from retention from CPU level */
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if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
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return;
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/* Get the mpidr for this cpu */
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mpidr = read_mpidr_el1();
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cluster = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFF1_SHIFT;
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cpu = mpidr & MPIDR_CPU_MASK;
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/* Enable CCI coherency for cluster */
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if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
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hisi_pwrc_set_core_bx_addr(cpu, cluster, 0);
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if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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} else {
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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}
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static void hikey_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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int i;
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for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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}
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static void __dead2 hikey_system_off(void)
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{
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NOTICE("%s: off system\n", __func__);
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/* Pull down GPIO_0_0 to trigger PMIC shutdown */
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mmio_write_32(0xF8001810, 0x2); /* Pinmux */
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mmio_write_8(0xF8011400, 1); /* Pin direction */
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mmio_write_8(0xF8011004, 0); /* Pin output value */
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/* Wait for 2s to power off system by PMIC */
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sp804_timer_init(SP804_TIMER0_BASE, 10, 192);
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mdelay(2000);
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/*
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* PMIC shutdown depends on two conditions: GPIO_0_0 (PWR_HOLD) low,
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* and VBUS_DET < 3.6V. For HiKey, VBUS_DET is connected to VDD_4V2
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* through Jumper 1-2. So, to complete shutdown, user needs to manually
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* remove Jumper 1-2.
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*/
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NOTICE("+------------------------------------------+\n");
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NOTICE("| IMPORTANT: Remove Jumper 1-2 to shutdown |\n");
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NOTICE("| DANGER: SoC is still burning. DANGER! |\n");
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NOTICE("| Board will be reboot to avoid overheat |\n");
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NOTICE("+------------------------------------------+\n");
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/* Send the system reset request */
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mmio_write_32(AO_SC_SYS_STAT0, 0x48698284);
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wfi();
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panic();
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}
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static void __dead2 hikey_system_reset(void)
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{
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/* Send the system reset request */
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@ -112,9 +208,6 @@ static void __dead2 hikey_system_reset(void)
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panic();
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}
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/*******************************************************************************
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* Handler called to check the validity of the power state parameter.
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******************************************************************************/
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int hikey_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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@ -153,9 +246,6 @@ int hikey_validate_power_state(unsigned int power_state,
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* Handler called to check the validity of the non secure entrypoint.
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******************************************************************************/
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static int hikey_validate_ns_entrypoint(uintptr_t entrypoint)
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{
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/*
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@ -168,26 +258,20 @@ static int hikey_validate_ns_entrypoint(uintptr_t entrypoint)
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return PSCI_E_INVALID_ADDRESS;
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}
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/*******************************************************************************
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* Export the platform handlers to enable psci to invoke them
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******************************************************************************/
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static const plat_psci_ops_t hikey_psci_ops = {
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.cpu_standby = NULL,
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.pwr_domain_on = hikey_pwr_domain_on,
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.pwr_domain_on_finish = hikey_pwr_domain_on_finish,
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.pwr_domain_off = hikey_pwr_domain_off,
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.pwr_domain_suspend = NULL,
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.pwr_domain_suspend_finish = NULL,
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.system_off = NULL,
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.pwr_domain_suspend = hikey_pwr_domain_suspend,
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.pwr_domain_suspend_finish = hikey_pwr_domain_suspend_finish,
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.system_off = hikey_system_off,
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.system_reset = hikey_system_reset,
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.validate_power_state = hikey_validate_power_state,
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.validate_ns_entrypoint = hikey_validate_ns_entrypoint,
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.get_sys_suspend_power_state = NULL,
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.get_sys_suspend_power_state = hikey_get_sys_suspend_power_state,
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};
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/*******************************************************************************
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* Export the platform specific power ops and initialize Power Controller
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******************************************************************************/
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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@ -197,6 +281,5 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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* Initialize PSCI ops struct
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*/
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*psci_ops = &hikey_psci_ops;
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return 0;
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}
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@ -18,8 +18,10 @@ const unsigned char hikey_power_domain_tree_desc[] = {
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1,
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/* Number of clusters */
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PLATFORM_CLUSTER_COUNT,
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/* Number of CPU cores */
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PLATFORM_CORE_COUNT
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/* Number of children for the first cluster node */
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PLATFORM_CORE_COUNT_PER_CLUSTER,
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/* Number of children for the second cluster node */
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PLATFORM_CORE_COUNT_PER_CLUSTER,
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};
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/*******************************************************************************
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@ -65,6 +65,8 @@ HIKEY_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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plat/common/plat_gicv2.c
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BL31_SOURCES += drivers/arm/cci/cci.c \
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drivers/arm/sp804/sp804_delay_timer.c \
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drivers/delay_timer/delay_timer.c \
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lib/cpus/aarch64/cortex_a53.S \
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plat/common/aarch64/plat_psci_common.c \
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plat/hisilicon/hikey/aarch64/hikey_helpers.S \
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