From 0d06b058a5bef1971ef7ebe7b9616b03fa7ecec8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Tue, 16 Feb 2021 11:56:24 +0100 Subject: [PATCH] marvell: uart: a3720: Increase TX FIFO EMPTY timeout from 2ms to 3ms MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TX FIFO has space for 32 characters. With default UART baudrate 115200 it takes more than 2ms to transmit all 32 characters, so wait at least 3ms before flushing TX FIFO. If WTMI firmware transmitted something via UART before TF-A was booted, some characters may still wait in TX FIFO when TF-A is initializing UART driver. So wait at least 3ms to ensure that HW has enough time to transmit all characters waiting in TX FIFO. This fixes an issue where sometimes characters transmitted on UART by our custom WTMI image are lost. Signed-off-by: Pali Rohár Change-Id: I8ea4ea58e4ba3e0c0d7f47e679171b9b94442f19 --- drivers/marvell/uart/a3700_console.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/marvell/uart/a3700_console.S b/drivers/marvell/uart/a3700_console.S index 9e74c33bb..b37732189 100644 --- a/drivers/marvell/uart/a3700_console.S +++ b/drivers/marvell/uart/a3700_console.S @@ -60,10 +60,10 @@ func console_a3700_core_init str w3, [x0, #UART_POSSR_REG] /* - * Wait for the TX (THR and TSR) to be empty. If wait for 2ms, the TX FIFO is + * Wait for the TX (THR and TSR) to be empty. If wait for 3ms, the TX FIFO is * still not empty, TX FIFO will reset by all means. */ - mov w1, #20 /* max time out 20 * 100 us */ + mov w1, #30 /* max time out 30 * 100 us */ 2: /* Check whether TX (THR and TSR) is empty */ ldr w3, [x0, #UART_STATUS_REG]