intel: s10: Remove unused source code
remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory as both has been refactored to common directory for sharing with agilex platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I395fed66408f536e8fefd637681e742c63621818
This commit is contained in:
Hadi Asyrafi
parent
ade3f5df96
commit
0d1b704ad8
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@ -1,208 +0,0 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <common/debug.h>
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#include <errno.h>
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#include <lib/mmio.h>
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#include <drivers/arm/gic_common.h>
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#include <drivers/arm/gicv2.h>
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#include <plat/common/platform.h>
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#include <lib/psci/psci.h>
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#include "platform_def.h"
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#include "s10_reset_manager.h"
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#include "socfpga_mailbox.h"
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#define S10_RSTMGR_OFST 0xffd11000
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#define S10_RSTMGR_MPUMODRST_OFST 0x20
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uintptr_t *stratix10_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY;
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uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE;
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/*******************************************************************************
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* plat handler called when a CPU is about to enter standby.
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******************************************************************************/
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void plat_cpu_standby(plat_local_state_t cpu_state)
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{
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/*
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* Enter standby state
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* dsb is good practice before using wfi to enter low power states
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*/
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VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state);
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dsb();
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wfi();
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}
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/*******************************************************************************
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* plat handler called when a power domain is about to be turned on. The
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* mpidr determines the CPU to be turned on.
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******************************************************************************/
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int plat_pwr_domain_on(u_register_t mpidr)
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{
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unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
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VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
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if (cpu_id == -1)
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return PSCI_E_INTERN_FAIL;
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*cpuid_release = cpu_id;
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/* release core reset */
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mmio_setbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST,
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1 << cpu_id);
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* plat handler called when a power domain is about to be turned off. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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void plat_pwr_domain_off(const psci_power_state_t *target_state)
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{
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unsigned int cpu_id = plat_my_core_pos();
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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/* TODO: Prevent interrupts from spuriously waking up this cpu */
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/* gicv2_cpuif_disable(); */
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/* assert core reset */
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mmio_setbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST,
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1 << cpu_id);
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}
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/*******************************************************************************
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* plat handler called when a power domain is about to be suspended. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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void plat_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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unsigned int cpu_id = plat_my_core_pos();
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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/* assert core reset */
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mmio_setbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST,
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1 << cpu_id);
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}
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/*******************************************************************************
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* plat handler called when a power domain has just been powered on after
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* being turned off earlier. The target_state encodes the low power state that
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* each level has woken up from.
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******************************************************************************/
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void plat_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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/* Program the gic per-cpu distributor or re-distributor interface */
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gicv2_pcpu_distif_init();
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gicv2_set_pe_target_mask(plat_my_core_pos());
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/* Enable the gic cpu interface */
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gicv2_cpuif_enable();
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}
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/*******************************************************************************
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* plat handler called when a power domain has just been powered on after
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* having been suspended earlier. The target_state encodes the low power state
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* that each level has woken up from.
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* TODO: At the moment we reuse the on finisher and reinitialize the secure
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* context. Need to implement a separate suspend finisher.
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******************************************************************************/
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void plat_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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unsigned int cpu_id = plat_my_core_pos();
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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/* release core reset */
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mmio_clrbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST,
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1 << cpu_id);
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}
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/*******************************************************************************
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* plat handlers to shutdown/reboot the system
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******************************************************************************/
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static void __dead2 plat_system_off(void)
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{
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wfi();
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ERROR("System Off: operation not handled.\n");
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panic();
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}
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static void __dead2 plat_system_reset(void)
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{
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INFO("assert Peripheral from Reset\r\n");
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deassert_peripheral_reset();
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mailbox_reset_cold();
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while (1)
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wfi();
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}
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int plat_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
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return PSCI_E_SUCCESS;
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}
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int plat_validate_ns_entrypoint(unsigned long ns_entrypoint)
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{
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VERBOSE("%s: ns_entrypoint: 0x%lx\n", __func__, ns_entrypoint);
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return PSCI_E_SUCCESS;
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}
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void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
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req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE;
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}
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/*******************************************************************************
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* Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
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* platform layer will take care of registering the handlers with PSCI.
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******************************************************************************/
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const plat_psci_ops_t plat_psci_pm_ops = {
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.cpu_standby = plat_cpu_standby,
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.pwr_domain_on = plat_pwr_domain_on,
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.pwr_domain_off = plat_pwr_domain_off,
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.pwr_domain_suspend = plat_pwr_domain_suspend,
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.pwr_domain_on_finish = plat_pwr_domain_on_finish,
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.pwr_domain_suspend_finish = plat_pwr_domain_suspend_finish,
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.system_off = plat_system_off,
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.system_reset = plat_system_reset,
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.validate_power_state = plat_validate_power_state,
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.validate_ns_entrypoint = plat_validate_ns_entrypoint,
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.get_sys_suspend_power_state = plat_get_sys_suspend_power_state
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};
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/*******************************************************************************
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* Export the platform specific power ops.
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******************************************************************************/
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const struct plat_psci_ops **psci_ops)
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{
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/* Save warm boot entrypoint.*/
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*stratix10_sec_entry = sec_entrypoint;
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*psci_ops = &plat_psci_pm_ops;
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return 0;
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}
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@ -1,378 +0,0 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <lib/mmio.h>
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#include <socfpga_mailbox.h>
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#include <tools_share/uuid.h>
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/* Number of SiP Calls implemented */
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#define SIP_NUM_CALLS 0x3
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/* Total buffer the driver can hold */
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#define FPGA_CONFIG_BUFFER_SIZE 4
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int current_block;
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int current_buffer;
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int current_id = 1;
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int max_blocks;
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uint32_t bytes_per_block;
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uint32_t blocks_submitted;
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uint32_t blocks_completed;
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struct fpga_config_info {
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uint32_t addr;
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int size;
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int size_written;
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uint32_t write_requested;
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int subblocks_sent;
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int block_number;
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};
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/* SiP Service UUID */
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DEFINE_SVC_UUID2(intl_svc_uid,
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0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a,
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0xfa, 0x88, 0x88, 0x17, 0x68, 0x81);
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uint64_t plat_sip_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x2,
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uint64_t x3,
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uint64_t x4,
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void *cookie,
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void *handle,
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uint64_t flags)
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{
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ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
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SMC_RET1(handle, SMC_UNK);
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}
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struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
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static void intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
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{
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uint32_t args[3];
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while (max_blocks > 0 && buffer->size > buffer->size_written) {
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if (buffer->size - buffer->size_written <=
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bytes_per_block) {
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args[0] = (1<<8);
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args[1] = buffer->addr + buffer->size_written;
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args[2] = buffer->size - buffer->size_written;
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buffer->size_written +=
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buffer->size - buffer->size_written;
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buffer->subblocks_sent++;
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mailbox_send_cmd_async(0x4,
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MBOX_RECONFIG_DATA,
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args, 3, 0);
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current_buffer++;
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current_buffer %= FPGA_CONFIG_BUFFER_SIZE;
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} else {
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args[0] = (1<<8);
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args[1] = buffer->addr + buffer->size_written;
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args[2] = bytes_per_block;
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buffer->size_written += bytes_per_block;
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mailbox_send_cmd_async(0x4,
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MBOX_RECONFIG_DATA,
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args, 3, 0);
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buffer->subblocks_sent++;
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}
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max_blocks--;
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}
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}
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static int intel_fpga_sdm_write_all(void)
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{
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int i;
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for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++)
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intel_fpga_sdm_write_buffer(
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&fpga_config_buffers[current_buffer]);
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return 0;
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}
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uint32_t intel_mailbox_fpga_config_isdone(void)
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{
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uint32_t args[2];
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uint32_t response[6];
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int status;
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status = mailbox_send_cmd(1, MBOX_RECONFIG_STATUS, args, 0, 0,
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response);
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if (status < 0)
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return INTEL_SIP_SMC_STATUS_ERROR;
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if (response[RECONFIG_STATUS_STATE] &&
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response[RECONFIG_STATUS_STATE] != MBOX_CFGSTAT_STATE_CONFIG)
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return INTEL_SIP_SMC_STATUS_ERROR;
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if (!(response[RECONFIG_STATUS_PIN_STATUS] & PIN_STATUS_NSTATUS))
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return INTEL_SIP_SMC_STATUS_ERROR;
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if (response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
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SOFTFUNC_STATUS_SEU_ERROR)
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return INTEL_SIP_SMC_STATUS_ERROR;
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if ((response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
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SOFTFUNC_STATUS_CONF_DONE) &&
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(response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
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SOFTFUNC_STATUS_INIT_DONE))
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return INTEL_SIP_SMC_STATUS_OK;
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return INTEL_SIP_SMC_STATUS_ERROR;
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}
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static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed)
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{
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int i;
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for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
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if (fpga_config_buffers[i].block_number == current_block) {
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fpga_config_buffers[i].subblocks_sent--;
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if (fpga_config_buffers[i].subblocks_sent == 0
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&& fpga_config_buffers[i].size <=
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fpga_config_buffers[i].size_written) {
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fpga_config_buffers[i].write_requested = 0;
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current_block++;
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*buffer_addr_completed =
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fpga_config_buffers[i].addr;
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return 0;
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}
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}
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}
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return -1;
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}
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unsigned int address_in_ddr(uint32_t *addr)
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{
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if (((unsigned long long)addr > DRAM_BASE) &&
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((unsigned long long)addr < DRAM_BASE + DRAM_SIZE))
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return 0;
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return -1;
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}
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int intel_fpga_config_completed_write(uint32_t *completed_addr,
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uint32_t *count)
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{
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uint32_t status = INTEL_SIP_SMC_STATUS_OK;
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*count = 0;
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int resp_len = 0;
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uint32_t resp[5];
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int all_completed = 1;
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int count_check = 0;
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if (address_in_ddr(completed_addr) != 0 || address_in_ddr(count) != 0)
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return INTEL_SIP_SMC_STATUS_ERROR;
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for (count_check = 0; count_check < 3; count_check++)
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if (address_in_ddr(&completed_addr[*count + count_check]) != 0)
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return INTEL_SIP_SMC_STATUS_ERROR;
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resp_len = mailbox_read_response(0x4, resp);
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while (resp_len >= 0 && *count < 3) {
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max_blocks++;
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if (mark_last_buffer_xfer_completed(
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&completed_addr[*count]) == 0)
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*count = *count + 1;
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else
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break;
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resp_len = mailbox_read_response(0x4, resp);
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}
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if (*count <= 0) {
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if (resp_len != MBOX_NO_RESPONSE &&
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resp_len != MBOX_TIMEOUT && resp_len != 0) {
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return INTEL_SIP_SMC_STATUS_ERROR;
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}
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*count = 0;
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}
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intel_fpga_sdm_write_all();
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if (*count > 0)
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status = INTEL_SIP_SMC_STATUS_OK;
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else if (*count == 0)
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status = INTEL_SIP_SMC_STATUS_BUSY;
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for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
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if (fpga_config_buffers[i].write_requested != 0) {
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all_completed = 0;
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break;
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}
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}
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if (all_completed == 1)
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return INTEL_SIP_SMC_STATUS_OK;
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return status;
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}
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int intel_fpga_config_start(uint32_t config_type)
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{
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uint32_t response[3];
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int status = 0;
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status = mailbox_send_cmd(2, MBOX_RECONFIG, 0, 0, 0,
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response);
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if (status < 0)
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return status;
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max_blocks = response[0];
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bytes_per_block = response[1];
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for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
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fpga_config_buffers[i].size = 0;
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fpga_config_buffers[i].size_written = 0;
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fpga_config_buffers[i].addr = 0;
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fpga_config_buffers[i].write_requested = 0;
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fpga_config_buffers[i].block_number = 0;
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fpga_config_buffers[i].subblocks_sent = 0;
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}
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blocks_submitted = 0;
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current_block = 0;
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current_buffer = 0;
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return 0;
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}
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uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
|
||||
{
|
||||
int i = 0;
|
||||
uint32_t status = INTEL_SIP_SMC_STATUS_OK;
|
||||
|
||||
if (mem < DRAM_BASE || mem > DRAM_BASE + DRAM_SIZE)
|
||||
status = INTEL_SIP_SMC_STATUS_REJECTED;
|
||||
|
||||
if (mem + size > DRAM_BASE + DRAM_SIZE)
|
||||
status = INTEL_SIP_SMC_STATUS_REJECTED;
|
||||
|
||||
for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
|
||||
if (!fpga_config_buffers[i].write_requested) {
|
||||
fpga_config_buffers[i].addr = mem;
|
||||
fpga_config_buffers[i].size = size;
|
||||
fpga_config_buffers[i].size_written = 0;
|
||||
fpga_config_buffers[i].write_requested = 1;
|
||||
fpga_config_buffers[i].block_number =
|
||||
blocks_submitted++;
|
||||
fpga_config_buffers[i].subblocks_sent = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if (i == FPGA_CONFIG_BUFFER_SIZE) {
|
||||
status = INTEL_SIP_SMC_STATUS_REJECTED;
|
||||
return status;
|
||||
} else if (i == FPGA_CONFIG_BUFFER_SIZE - 1) {
|
||||
status = INTEL_SIP_SMC_STATUS_BUSY;
|
||||
}
|
||||
|
||||
intel_fpga_sdm_write_all();
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is responsible for handling all SiP calls from the NS world
|
||||
*/
|
||||
|
||||
uintptr_t sip_smc_handler(uint32_t smc_fid,
|
||||
u_register_t x1,
|
||||
u_register_t x2,
|
||||
u_register_t x3,
|
||||
u_register_t x4,
|
||||
void *cookie,
|
||||
void *handle,
|
||||
u_register_t flags)
|
||||
{
|
||||
uint32_t status = INTEL_SIP_SMC_STATUS_OK;
|
||||
uint32_t completed_addr[3];
|
||||
uint32_t count = 0;
|
||||
|
||||
switch (smc_fid) {
|
||||
case SIP_SVC_UID:
|
||||
/* Return UID to the caller */
|
||||
SMC_UUID_RET(handle, intl_svc_uid);
|
||||
break;
|
||||
case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
|
||||
status = intel_mailbox_fpga_config_isdone();
|
||||
SMC_RET4(handle, status, 0, 0, 0);
|
||||
break;
|
||||
case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
|
||||
SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
|
||||
INTEL_SIP_SMC_FPGA_CONFIG_ADDR,
|
||||
INTEL_SIP_SMC_FPGA_CONFIG_SIZE -
|
||||
INTEL_SIP_SMC_FPGA_CONFIG_ADDR);
|
||||
break;
|
||||
case INTEL_SIP_SMC_FPGA_CONFIG_START:
|
||||
status = intel_fpga_config_start(x1);
|
||||
SMC_RET4(handle, status, 0, 0, 0);
|
||||
break;
|
||||
case INTEL_SIP_SMC_FPGA_CONFIG_WRITE:
|
||||
status = intel_fpga_config_write(x1, x2);
|
||||
SMC_RET4(handle, status, 0, 0, 0);
|
||||
break;
|
||||
case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE:
|
||||
status = intel_fpga_config_completed_write(completed_addr,
|
||||
&count);
|
||||
switch (count) {
|
||||
case 1:
|
||||
SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
|
||||
completed_addr[0], 0, 0);
|
||||
break;
|
||||
case 2:
|
||||
SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
|
||||
completed_addr[0],
|
||||
completed_addr[1], 0);
|
||||
break;
|
||||
case 3:
|
||||
SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
|
||||
completed_addr[0],
|
||||
completed_addr[1],
|
||||
completed_addr[2]);
|
||||
break;
|
||||
case 0:
|
||||
SMC_RET4(handle, status, 0, 0, 0);
|
||||
break;
|
||||
default:
|
||||
SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
return plat_sip_handler(smc_fid, x1, x2, x3, x4,
|
||||
cookie, handle, flags);
|
||||
}
|
||||
}
|
||||
|
||||
DECLARE_RT_SVC(
|
||||
s10_sip_svc,
|
||||
OEN_SIP_START,
|
||||
OEN_SIP_END,
|
||||
SMC_TYPE_FAST,
|
||||
NULL,
|
||||
sip_smc_handler
|
||||
);
|
||||
|
||||
DECLARE_RT_SVC(
|
||||
s10_sip_svc_std,
|
||||
OEN_SIP_START,
|
||||
OEN_SIP_END,
|
||||
SMC_TYPE_YIELD,
|
||||
NULL,
|
||||
sip_smc_handler
|
||||
);
|
||||
Loading…
Reference in New Issue