Rename PLAT_ARM_BL31_RUN_UART* variable
The variable is renamed to PLAT_ARM_RUN_UART as the UART is used outside BL31 as well. Change-Id: I00e3639dfb2001758b7d24548c11236c6335f64a Signed-off-by: Usama Arif <usama.arif@arm.com>
This commit is contained in:
parent
fa233ac9d4
commit
0d28096cd7
|
@ -61,14 +61,14 @@
|
||||||
#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE
|
#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE
|
||||||
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ
|
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ
|
||||||
|
|
||||||
#define PLAT_ARM_BL31_RUN_UART_BASE SOC_CSS_UART1_BASE
|
#define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE
|
||||||
#define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
|
#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
|
||||||
|
|
||||||
#define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE
|
#define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE
|
||||||
#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
|
#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
|
||||||
|
|
||||||
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE
|
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
|
||||||
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ
|
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
|
||||||
|
|
||||||
#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE
|
#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE
|
||||||
#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
|
#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
|
||||||
|
|
|
@ -173,14 +173,14 @@
|
||||||
#define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE
|
#define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE
|
||||||
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
|
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
|
||||||
|
|
||||||
#define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE
|
#define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE
|
||||||
#define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
|
#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
|
||||||
|
|
||||||
#define PLAT_ARM_SP_MIN_RUN_UART_BASE V2M_IOFPGA_UART1_BASE
|
#define PLAT_ARM_SP_MIN_RUN_UART_BASE V2M_IOFPGA_UART1_BASE
|
||||||
#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
|
#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
|
||||||
|
|
||||||
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE
|
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
|
||||||
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ
|
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
|
||||||
|
|
||||||
#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE
|
#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE
|
||||||
#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ
|
#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ
|
||||||
|
|
|
@ -15,14 +15,14 @@
|
||||||
#define PLAT_ARM_BOOT_UART_BASE 0x2A400000
|
#define PLAT_ARM_BOOT_UART_BASE 0x2A400000
|
||||||
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 50000000
|
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 50000000
|
||||||
|
|
||||||
#define PLAT_ARM_BL31_RUN_UART_BASE 0x2A410000
|
#define PLAT_ARM_RUN_UART_BASE 0x2A410000
|
||||||
#define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ 50000000
|
#define PLAT_ARM_RUN_UART_CLK_IN_HZ 50000000
|
||||||
|
|
||||||
#define PLAT_ARM_SP_MIN_RUN_UART_BASE 0x2A410000
|
#define PLAT_ARM_SP_MIN_RUN_UART_BASE 0x2A410000
|
||||||
#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ 50000000
|
#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ 50000000
|
||||||
|
|
||||||
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE
|
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
|
||||||
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ
|
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
|
||||||
|
|
||||||
#define PLAT_ARM_DRAM2_SIZE ULL(0x780000000)
|
#define PLAT_ARM_DRAM2_SIZE ULL(0x780000000)
|
||||||
|
|
||||||
|
|
|
@ -61,8 +61,8 @@ void arm_console_boot_end(void)
|
||||||
void arm_console_runtime_init(void)
|
void arm_console_runtime_init(void)
|
||||||
{
|
{
|
||||||
#if MULTI_CONSOLE_API
|
#if MULTI_CONSOLE_API
|
||||||
int rc = console_pl011_register(PLAT_ARM_BL31_RUN_UART_BASE,
|
int rc = console_pl011_register(PLAT_ARM_RUN_UART_BASE,
|
||||||
PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ,
|
PLAT_ARM_RUN_UART_CLK_IN_HZ,
|
||||||
ARM_CONSOLE_BAUDRATE,
|
ARM_CONSOLE_BAUDRATE,
|
||||||
&arm_runtime_console);
|
&arm_runtime_console);
|
||||||
if (rc == 0)
|
if (rc == 0)
|
||||||
|
@ -70,8 +70,8 @@ void arm_console_runtime_init(void)
|
||||||
|
|
||||||
console_set_scope(&arm_runtime_console.console, CONSOLE_FLAG_RUNTIME);
|
console_set_scope(&arm_runtime_console.console, CONSOLE_FLAG_RUNTIME);
|
||||||
#else
|
#else
|
||||||
(void)console_init(PLAT_ARM_BL31_RUN_UART_BASE,
|
(void)console_init(PLAT_ARM_RUN_UART_BASE,
|
||||||
PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ,
|
PLAT_ARM_RUN_UART_CLK_IN_HZ,
|
||||||
ARM_CONSOLE_BAUDRATE);
|
ARM_CONSOLE_BAUDRATE);
|
||||||
#endif /* MULTI_CONSOLE_API */
|
#endif /* MULTI_CONSOLE_API */
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue