andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merge changes from topic "tegra-downstream-07092020" into integration 

* changes:
  Tegra194: remove AON_WDT IRQ mapping
  Tegra: smmu: add smmu_verify function
  Tegra: TZDRAM setup from soc specific early_boot handlers
  Tegra: remove "platform_get_core_pos" function
  Tegra: print GICC registers conditionally
  lib: cpus: sanity check pointers before use
  Tegra: spe: do not flush console in console_putc
  Tegra: verify platform compatibility
This commit is contained in:
Varun Wadekar 2020-08-25 03:27:26 +00:00 committed by TrustedFirmware Code Review
parent 2b4103f786 be41aac7a7
commit 0d5caf958c
12 changed files with 143 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
lib/cpus/aarch64/cpu_helpers.S
View File

@ -78,6 +78,10 @@ func prepare_cpu_pwr_dwn
mov x1, #CPU_PWR_DWN_OPS
add x1, x1, x2, lsl #3
ldr x1, [x0, x1]
#if ENABLE_ASSERTIONS
cmp x1, #0
ASM_ASSERT(ne)
#endif
br x1
endfunc prepare_cpu_pwr_dwn
@ -171,6 +175,10 @@ func get_cpu_ops_ptr
/* Subtract the increment and offset to get the cpu-ops pointer */
sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR)
#if ENABLE_ASSERTIONS
cmp x0, #0
ASM_ASSERT(ne)
#endif
error_exit:
ret
endfunc get_cpu_ops_ptr
@ -276,7 +284,15 @@ func print_errata_status
* turn.
*/
mrs x0, tpidr_el3
#if ENABLE_ASSERTIONS
cmp x0, #0
ASM_ASSERT(ne)
#endif
ldr x1, [x0, #CPU_DATA_CPU_OPS_PTR]
#if ENABLE_ASSERTIONS
cmp x1, #0
ASM_ASSERT(ne)
#endif
ldr x0, [x1, #CPU_ERRATA_FUNC]
cbz x0, .Lnoprint
@ -326,6 +342,10 @@ func check_wa_cve_2017_5715
ASM_ASSERT(ne)
#endif
ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR]
#if ENABLE_ASSERTIONS
cmp x0, #0
ASM_ASSERT(ne)
#endif
ldr x0, [x0, #CPU_EXTRA1_FUNC]
/*
* If the reserved function pointer is NULL, this CPU
@ -359,6 +379,10 @@ func wa_cve_2018_3639_get_disable_ptr
ASM_ASSERT(ne)
#endif
ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR]
#if ENABLE_ASSERTIONS
cmp x0, #0
ASM_ASSERT(ne)
#endif
ldr x0, [x0, #CPU_EXTRA2_FUNC]
ret
endfunc wa_cve_2018_3639_get_disable_ptr

17
plat/nvidia/tegra/common/aarch64/tegra_helpers.S
View File

@ -166,23 +166,6 @@ func plat_get_my_entrypoint
ret
endfunc plat_get_my_entrypoint
/* -----------------------------------------------------
* int platform_get_core_pos(int mpidr);
*
* result: CorePos = (ClusterId * cpus per cluster) +
* CoreId
* -----------------------------------------------------
*/
func platform_get_core_pos
and x1, x0, #MPIDR_CPU_MASK
and x0, x0, #MPIDR_CLUSTER_MASK
lsr x0, x0, #MPIDR_AFFINITY_BITS
mov x2, #PLATFORM_MAX_CPUS_PER_CLUSTER
mul x0, x0, x2
add x0, x1, x0
ret
endfunc platform_get_core_pos
/* -----------------------------------------------------
* void plat_secondary_cold_boot_setup (void);
*

23
plat/nvidia/tegra/common/tegra_bl31_setup.c
View File

@ -28,6 +28,7 @@
#include <memctrl.h>
#include <profiler.h>
#include <smmu.h>
#include <tegra_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
@ -179,21 +180,6 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
/* Early platform setup for Tegra SoCs */
plat_early_platform_setup();
/*
* Do initial security configuration to allow DRAM/device access.
*/
tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
(uint32_t)plat_bl31_params_from_bl2.tzdram_size);
#if RELOCATE_BL32_IMAGE
/*
* The previous bootloader might not have placed the BL32 image
* inside the TZDRAM. Platform handler to allow relocation of BL32
* image to TZDRAM memory. This behavior might change per platform.
*/
plat_relocate_bl32_image(arg_from_bl2->bl32_image_info);
#endif
/*
* Add timestamp for platform early setup exit.
*/
@ -287,6 +273,13 @@ void bl31_plat_runtime_setup(void)
*/
tegra_memctrl_disable_ahb_redirection();
#if defined(TEGRA_SMMU0_BASE)
/*
* Verify the integrity of the previously configured SMMU(s) settings
*/
tegra_smmu_verify();
#endif
/*
* Add final timestamp before exiting BL31.
*/

62
plat/nvidia/tegra/drivers/smmu/smmu.c
View File

@ -14,6 +14,7 @@
#include <common/debug.h>
#include <smmu.h>
#include <tegra_platform.h>
#include <tegra_private.h>
extern void memcpy16(void *dest, const void *src, unsigned int length);
@ -21,15 +22,17 @@ extern void memcpy16(void *dest, const void *src, unsigned int length);
#define SMMU_NUM_CONTEXTS 64U
#define SMMU_CONTEXT_BANK_MAX_IDX 64U
#define MISMATCH_DETECTED 0x55AA55AAU
/*
* Init SMMU during boot or "System Suspend" exit
*/
void tegra_smmu_init(void)
{
uint32_t val, cb_idx, smmu_id, ctx_base;
uint32_t smmu_counter = plat_get_num_smmu_devices();
uint32_t num_smmu_devices = plat_get_num_smmu_devices();
for (smmu_id = 0U; smmu_id < smmu_counter; smmu_id++) {
for (smmu_id = 0U; smmu_id < num_smmu_devices; smmu_id++) {
/* Program the SMMU pagesize and reset CACHE_LOCK bit */
val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
val |= SMMU_GSR0_PGSIZE_64K;
@ -44,7 +47,7 @@ void tegra_smmu_init(void)
/* disable TCU prefetch for all contexts */
ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS)
+ SMMU_CBn_ACTLR;
for (cb_idx = 0; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) {
for (cb_idx = 0U; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) {
val = tegra_smmu_read_32(smmu_id,
ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx));
val &= (uint32_t)~SMMU_CBn_ACTLR_CPRE_BIT;
@ -63,3 +66,56 @@ void tegra_smmu_init(void)
tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
}
}
/*
* Verify SMMU settings have not been altered during boot
*/
void tegra_smmu_verify(void)
{
uint32_t cb_idx, ctx_base, smmu_id, val;
uint32_t num_smmu_devices = plat_get_num_smmu_devices();
uint32_t mismatch = 0U;
for (smmu_id = 0U; smmu_id < num_smmu_devices; smmu_id++) {
/* check PGSIZE_64K bit inr S Aux. Config. Register */
val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
if (0U == (val & SMMU_GSR0_PGSIZE_64K)) {
ERROR("%s: PGSIZE_64K Mismatch - smmu_id=%d, GSR0_SECURE_ACR=%x\n",
__func__, smmu_id, val);
mismatch = MISMATCH_DETECTED;
}
/* check CACHE LOCK bit in S Aux. Config. Register */
if (0U == (val & SMMU_ACR_CACHE_LOCK_ENABLE_BIT)) {
ERROR("%s: CACHE_LOCK Mismatch - smmu_id=%d, GSR0_SECURE_ACR=%x\n",
__func__, smmu_id, val);
mismatch = MISMATCH_DETECTED;
}
/* check CACHE LOCK bit in NS Aux. Config. Register */
val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
if (0U == (val & SMMU_ACR_CACHE_LOCK_ENABLE_BIT)) {
ERROR("%s: Mismatch - smmu_id=%d, GNSR_ACR=%x\n",
__func__, smmu_id, val);
mismatch = MISMATCH_DETECTED;
}
/* verify TCU prefetch for all contexts is disabled */
ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS) +
SMMU_CBn_ACTLR;
for (cb_idx = 0U; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) {
val = tegra_smmu_read_32(smmu_id,
ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx));
if (0U != (val & SMMU_CBn_ACTLR_CPRE_BIT)) {
ERROR("%s: Mismatch - smmu_id=%d, cb_idx=%d, GSR0_PGSIZE_64K=%x\n",
__func__, smmu_id, cb_idx, val);
mismatch = MISMATCH_DETECTED;
}
}
}
/* Treat configuration mismatch as fatal */
if ((mismatch == MISMATCH_DETECTED) && tegra_platform_is_silicon()) {
panic();
}
}

9
plat/nvidia/tegra/drivers/spe/shared_console.S
View File

@ -11,8 +11,7 @@
#define CONSOLE_FLUSH_DATA_TO_PORT (1 << 26)
#define CONSOLE_RING_DOORBELL (1 << 31)
#define CONSOLE_IS_BUSY (1 << 31)
#define CONSOLE_TIMEOUT 0xC000 /* approx. 50 ms */
#define CONSOLE_WRITE (CONSOLE_RING_DOORBELL | CONSOLE_FLUSH_DATA_TO_PORT)
#define CONSOLE_TIMEOUT 0xC000 /* 50 ms */
/*
* This file contains a driver implementation to make use of the
@ -101,7 +100,7 @@ func console_spe_core_putc
/* spe is ready */
mov w2, #0xD /* '\r' */
and w2, w2, #0xFF
mov w3, #(CONSOLE_WRITE | (1 << CONSOLE_NUM_BYTES_SHIFT))
mov w3, #(CONSOLE_RING_DOORBELL | (1 << CONSOLE_NUM_BYTES_SHIFT))
orr w2, w2, w3
str w2, [x1]
@ -111,7 +110,7 @@ not_eol:
/* spe is ready */
mov w2, w0
and w2, w2, #0xFF
mov w3, #(CONSOLE_WRITE | (1 << CONSOLE_NUM_BYTES_SHIFT))
mov w3, #(CONSOLE_RING_DOORBELL | (1 << CONSOLE_NUM_BYTES_SHIFT))
orr w2, w2, w3
str w2, [x1]
@ -164,7 +163,7 @@ func console_spe_core_flush
cbz x0, flush_error
/* flush console */
mov w1, #CONSOLE_WRITE
mov w1, #(CONSOLE_RING_DOORBELL | CONSOLE_FLUSH_DATA_TO_PORT)
str w1, [x0]
mov w0, #0
ret

2
plat/nvidia/tegra/include/drivers/memctrl_v2.h
View File

@ -144,6 +144,7 @@ static inline void tegra_mc_write_32(uint32_t off, uint32_t val)
mmio_write_32(TEGRA_MC_BASE + off, val);
}
#if defined(TEGRA_MC_STREAMID_BASE)
static inline uint32_t tegra_mc_streamid_read_32(uint32_t off)
{
return mmio_read_32(TEGRA_MC_STREAMID_BASE + off);
@ -153,6 +154,7 @@ static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val)
{
mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val);
}
#endif
#define mc_set_pcfifo_unordered_boot_so_mss(id, client) \
((uint32_t)~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \

1
plat/nvidia/tegra/include/drivers/smmu.h
View File

@ -86,6 +86,7 @@ static inline void tegra_smmu_write_32(uint32_t smmu_id,
}
void tegra_smmu_init(void);
void tegra_smmu_verify(void);
uint32_t plat_get_num_smmu_devices(void);
#endif /* SMMU_H */

4
plat/nvidia/tegra/include/plat_macros.S
View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -27,6 +28,7 @@ spacer:
* ---------------------------------------------
*/
.macro plat_crash_print_regs
#ifdef TEGRA_GICC_BASE
mov_imm x16, TEGRA_GICC_BASE
/* gicc base address is now in x16 */
@ -37,7 +39,7 @@ spacer:
ldr w10, [x16, #GICC_CTLR]
/* Store to the crash buf and print to cosole */
bl str_in_crash_buf_print
#endif
/* Print the GICD_ISPENDR regs */
mov_imm x16, TEGRA_GICD_BASE
add x7, x16, #GICD_ISPENDR

13
plat/nvidia/tegra/soc/t132/plat_setup.c
View File

@ -6,9 +6,11 @@
*/
#include <arch_helpers.h>
#include <assert.h>
#include <common/bl_common.h>
#include <drivers/console.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <memctrl.h>
#include <plat/common/platform.h>
#include <tegra_def.h>
#include <tegra_platform.h>
@ -144,7 +146,16 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
******************************************************************************/
void plat_early_platform_setup(void)
{
; /* do nothing */
plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
/* Verify chip id is t132 */
assert(tegra_chipid_is_t132());
/*
* Do initial security configuration to allow DRAM/device access.
*/
tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
(uint32_t)plat_params->tzdram_size);
}
/*******************************************************************************

18
plat/nvidia/tegra/soc/t186/plat_setup.c
View File

@ -26,6 +26,7 @@
#include <plat/common/platform.h>
#include <mce.h>
#include <memctrl.h>
#include <tegra_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
@ -185,10 +186,20 @@ void plat_early_platform_setup(void)
{
uint64_t impl, val;
const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
const struct tegra_bl31_params *arg_from_bl2 = plat_get_bl31_params();
/* Verify chip id is t186 */
assert(tegra_chipid_is_t186());
/* sanity check MCE firmware compatibility */
mce_verify_firmware_version();
/*
* Do initial security configuration to allow DRAM/device access.
*/
tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
(uint32_t)plat_params->tzdram_size);
impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK;
/*
@ -202,6 +213,13 @@ void plat_early_platform_setup(void)
val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
write_l2ctlr_el1(val);
}
/*
* The previous bootloader might not have placed the BL32 image
* inside the TZDRAM. Platform handler to allow relocation of BL32
* image to TZDRAM memory. This behavior might change per platform.
*/
plat_relocate_bl32_image(arg_from_bl2->bl32_image_info);
}
/*******************************************************************************

5
plat/nvidia/tegra/soc/t194/plat_setup.c
View File

@ -205,6 +205,9 @@ void plat_early_platform_setup(void)
uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step;
uint64_t actlr_elx;
/* Verify chip id is t194 */
assert(tegra_chipid_is_t194());
/* sanity check MCE firmware compatibility */
mce_verify_firmware_version();
@ -283,8 +286,6 @@ static const interrupt_prop_t tegra194_interrupt_props[] = {
INTR_PROP_DESC(TEGRA_SDEI_SGI_PRIVATE, PLAT_SDEI_CRITICAL_PRI,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
INTR_PROP_DESC(TEGRA194_AON_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
};

9
plat/nvidia/tegra/soc/t210/plat_setup.c
View File

@ -165,6 +165,15 @@ void plat_early_platform_setup(void)
const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
uint64_t val;
/* Verify chip id is t210 */
assert(tegra_chipid_is_t210());
/*
* Do initial security configuration to allow DRAM/device access.
*/
tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
(uint32_t)plat_params->tzdram_size);
/* platform parameter passed by the previous bootloader */
if (plat_params->l2_ecc_parity_prot_dis != 1) {
/* Enable ECC Parity Protection for Cortex-A57 CPUs */