Merge "meson: gxl: Fix CPU hotplug" into integration
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commit
0d7b0963cf
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@ -162,7 +162,8 @@ static void gxbb_pwr_domain_off(const psci_power_state_t *target_state)
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static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t
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static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t
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*target_state)
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*target_state)
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{
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{
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unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1());
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u_register_t mpidr = read_mpidr_el1();
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unsigned int core = plat_gxbb_calc_core_pos(mpidr);
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/* CPU0 can't be turned OFF, emulate it with a WFE loop */
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/* CPU0 can't be turned OFF, emulate it with a WFE loop */
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if (core == GXBB_PRIMARY_CPU) {
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if (core == GXBB_PRIMARY_CPU) {
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@ -173,10 +174,19 @@ static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t
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VERBOSE("BL31: CPU0 resumed.\n");
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VERBOSE("BL31: CPU0 resumed.\n");
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write_rmr_el3(RMR_EL3_RR_BIT | RMR_EL3_AA64_BIT);
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/*
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* Because setting CPU0's warm reset entrypoint through PSCI
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* mailbox and/or mmio mapped RVBAR (0xda834650) does not seem
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* to work, jump to it manually.
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* In order to avoid an assert, mmu has to be disabled.
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*/
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disable_mmu_el3();
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((void(*)(void))gxbb_sec_entrypoint)();
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}
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}
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dsbsy();
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dsbsy();
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gxl_pm_set_reset_addr(mpidr, 0);
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gxl_pm_reset(mpidr);
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for (;;)
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for (;;)
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wfi();
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wfi();
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