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fix(drivers/rcar3): fix CPG registers redefinition 

This commit deletes the value of the redefined CPG register.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I05cf4a449ae28adb2ddd59593971a7d0cbcb21de
This commit is contained in:
Toshiyuki Ogasahara 2020-11-30 20:39:21 +09:00 committed by Marek Vasut
parent 36d5645aec
commit 0dae56bb2f
7 changed files with 21 additions and 26 deletions
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5
drivers/renesas/common/common.c
View File

@ -1,11 +1,12 @@
/*
* Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <lib/mmio.h>
#include "cpg_registers.h"
#include "rcar_private.h"
#if IMAGE_BL31
@ -16,7 +17,7 @@ void cpg_write(uintptr_t regadr, uint32_t regval)
{
uint32_t value = regval;
mmio_write_32((uintptr_t) RCAR_CPGWPR, ~value);
mmio_write_32(CPG_CPGWPR, ~value);
mmio_write_32(regadr, value);
}

6
drivers/renesas/common/emmc/emmc_init.c
View File

@ -88,11 +88,11 @@ static EMMC_ERROR_CODE emmc_dev_finalize(void)
SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */
SETR_32(SD_CLK_CTRL, 0x00000000U); /* MMC clock stop */
dataL = mmio_read_32(CPG_SMSTPCR3);
dataL = mmio_read_32(SMSTPCR3);
if ((dataL & CPG_MSTP_MMC) == 0U) {
dataL |= (CPG_MSTP_MMC);
mmio_write_32(CPG_CPGWPR, (~dataL));
mmio_write_32(CPG_SMSTPCR3, dataL);
mmio_write_32(SMSTPCR3, dataL);
}
return result;
@ -101,7 +101,7 @@ static EMMC_ERROR_CODE emmc_dev_finalize(void)
static EMMC_ERROR_CODE emmc_dev_init(void)
{
/* Enable clock supply to eMMC. */
mstpcr_write(CPG_SMSTPCR3, CPG_MSTPSR3, CPG_MSTP_MMC);
mstpcr_write(SMSTPCR3, CPG_MSTPSR3, CPG_MSTP_MMC);
/* Set SD clock */
mmio_write_32(CPG_CPGWPR, ~((uint32_t) (BIT9 | BIT0))); /* SD phy 200MHz */

11
drivers/renesas/common/emmc/emmc_registers.h
View File

@ -50,17 +50,6 @@
#define BIT30 (0x40000000U)
#define BIT31 (0x80000000U)
/* Clock Pulse Generator (CPG) registers */
#define CPG_BASE (0xE6150000U)
/* Module stop status register 3 */
#define CPG_MSTPSR3 (CPG_BASE + 0x0048U)
/* System module stop control register 3 */
#define CPG_SMSTPCR3 (CPG_BASE + 0x013CU)
/* SDHI2 clock frequency control register */
#define CPG_SD2CKCR (CPG_BASE + 0x0268U)
/* SDHI3 clock frequency control register */
#define CPG_SD3CKCR (CPG_BASE + 0x026CU)
#if USE_MMC_CH == MMC_CH0
#define CPG_SDxCKCR (CPG_SD2CKCR) /* SDHI2/MMC0 */
#else /* USE_MMC_CH == MMC_CH0 */

7
drivers/renesas/common/pwrc/pwrc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -20,6 +20,7 @@
#include "pwrc.h"
#include "rcar_def.h"
#include "rcar_private.h"
#include "cpg_registers.h"
/*
* Someday there will be a generic power controller api. At the moment each
@ -238,7 +239,7 @@ void rcar_pwrc_cpuon(uint64_t mpidr)
scu_power_up(mpidr);
cpu = mpidr & MPIDR_CPU_MASK;
on_data = 1 << cpu;
mmio_write_32(RCAR_CPGWPR, ~on_data);
mmio_write_32(CPG_CPGWPR, ~on_data);
mmio_write_32(on_reg, on_data);
mmio_write_32(res_reg, res_data & (~(1 << (3 - cpu))));
@ -260,7 +261,7 @@ void rcar_pwrc_cpuoff(uint64_t mpidr)
if (read_mpidr_el1() != mpidr)
panic();
mmio_write_32(RCAR_CPGWPR, ~CPU_PWR_OFF);
mmio_write_32(CPG_CPGWPR, ~CPU_PWR_OFF);
mmio_write_32(reg + cpu * 0x0010, CPU_PWR_OFF);
rcar_lock_release();

3
plat/renesas/common/include/rcar_def.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -120,7 +120,6 @@
/* Timer control */
#define RCAR_CNTC_BASE U(0xE6080000)
/* Reset */
#define RCAR_CPGWPR U(0xE6150900) /* CPG write protect */
#define RCAR_MODEMR U(0xE6160060) /* Mode pin */
#define RCAR_CA57RESCNT U(0xE6160040) /* Reset control A57 */
#define RCAR_CA53RESCNT U(0xE6160044) /* Reset control A53 */

8
plat/renesas/common/include/registers/cpg_registers.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -16,6 +16,8 @@
#define CPG_SRCR2 (CPG_BASE + 0x00B0U)
/* CPG module stop status 2 */
#define CPG_MSTPSR2 (CPG_BASE + 0x0040U)
/* CPG module stop status 2 */
#define CPG_MSTPSR3 (CPG_BASE + 0x0048U)
/* CPG write protect */
#define CPG_CPGWPR (CPG_BASE + 0x0900U)
/* CPG write protect control */
@ -24,6 +26,10 @@
#define CPG_SMSTPCR9 (CPG_BASE + 0x0994U)
/* CPG module stop status 9 */
#define CPG_MSTPSR9 (CPG_BASE + 0x09A4U)
/* SDHI2 clock frequency control register */
#define CPG_SD2CKCR (CPG_BASE + 0x0268U)
/* SDHI3 clock frequency control register */
#define CPG_SD3CKCR (CPG_BASE + 0x026CU)
/* CPG (SECURITY) registers */

7
plat/renesas/common/rcar_common.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2019-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -12,9 +12,8 @@
#include <plat/common/platform.h>
#include <lib/mmio.h>
#include <cpg_registers.h>
#define CPG_BASE 0xE6150000
#define CPG_MSTPSR3 0x0048
#define MSTP318 (1 << 18)
#define MSTP319 (1 << 19)
#define PMSR 0x5c
@ -31,7 +30,7 @@ static int rcar_pcie_fixup(unsigned int controller)
int ret = 0;
/* Test if PCIECx is enabled */
cpg = mmio_read_32(CPG_BASE + CPG_MSTPSR3);
cpg = mmio_read_32(CPG_MSTPSR3);
if (cpg & (MSTP318 << !controller))
return ret;