From efeb43808d2e3ed23e1d51d5e86460db92971e96 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Mon, 9 Aug 2021 09:38:58 +0530 Subject: [PATCH] feat(rdn2): add board support for rdn2cfg2 variant Add board support for variant 2 of RD-N2 platform which is a four chip variant with 4 cores on each chip. The "CSS_SGI_PLATFORM_VARIANT" value is 2 for multi-chip variant. The "CSS_SGI_CHIP_COUNT_MACRO" can be in the range [1, 4] for multi-chip variant. Signed-off-by: Aditya Angadi Change-Id: I6412106e80e2f17704c796226c2ee9fe808705ba --- plat/arm/board/rdn2/include/platform_def.h | 16 ++- plat/arm/board/rdn2/platform.mk | 32 +++-- plat/arm/board/rdn2/rdn2_plat.c | 109 +++++++++++++++++- plat/arm/board/rdn2/rdn2_security.c | 46 +++++++- plat/arm/board/rdn2/rdn2_topology.c | 37 +++++- plat/arm/css/sgi/include/sgi_soc_css_def_v2.h | 6 + plat/arm/css/sgi/sgi_plat_v2.c | 9 ++ 7 files changed, 239 insertions(+), 16 deletions(-) diff --git a/plat/arm/board/rdn2/include/platform_def.h b/plat/arm/board/rdn2/include/platform_def.h index 194814f95..e4015f75b 100644 --- a/plat/arm/board/rdn2/include/platform_def.h +++ b/plat/arm/board/rdn2/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,6 +13,8 @@ #if (CSS_SGI_PLATFORM_VARIANT == 1) #define PLAT_ARM_CLUSTER_COUNT U(8) +#elif (CSS_SGI_PLATFORM_VARIANT == 2) +#define PLAT_ARM_CLUSTER_COUNT U(4) #else #define PLAT_ARM_CLUSTER_COUNT U(16) #endif @@ -34,6 +36,8 @@ #if (CSS_SGI_PLATFORM_VARIANT == 1) #define TZC400_COUNT U(2) +#elif (CSS_SGI_PLATFORM_VARIANT == 2) +#define TZC400_COUNT U(4) #else #define TZC400_COUNT U(8) #endif @@ -64,8 +68,15 @@ * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ #ifdef __aarch64__ +#if (CSS_SGI_PLATFORM_VARIANT == 2) +#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ + CSS_SGI_CHIP_COUNT) +#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ + CSS_SGI_CHIP_COUNT) +#else #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42) +#endif #else #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) @@ -75,6 +86,9 @@ #define PLAT_ARM_GICD_BASE UL(0x30000000) #define PLAT_ARM_GICC_BASE UL(0x2C000000) +/* Virtual address used by dynamic mem_protect for chunk_base */ +#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000) + #if (CSS_SGI_PLATFORM_VARIANT == 1) #define PLAT_ARM_GICR_BASE UL(0x30100000) #else diff --git a/plat/arm/board/rdn2/platform.mk b/plat/arm/board/rdn2/platform.mk index 5b24c32bd..753ba3237 100644 --- a/plat/arm/board/rdn2/platform.mk +++ b/plat/arm/board/rdn2/platform.mk @@ -3,9 +3,27 @@ # SPDX-License-Identifier: BSD-3-Clause # +RD_N2_VARIANTS := 0 1 2 +ifneq ($(CSS_SGI_PLATFORM_VARIANT),\ + $(filter $(CSS_SGI_PLATFORM_VARIANT),$(RD_N2_VARIANTS))) + $(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should be 0, 1 or 2, currently set \ + to ${CSS_SGI_PLATFORM_VARIANT}.") +endif + +$(eval $(call CREATE_SEQ,SEQ,4)) +ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ))) + $(error "Chip count for RD-N2-MC should be either $(SEQ) \ + currently it is set to ${CSS_SGI_CHIP_COUNT}.") +endif + # RD-N2 platform uses GIC-700 which is based on GICv4.1 GIC_ENABLE_V4_EXTN := 1 +#Enable GIC Multichip Extension only for Multichip Platforms +ifeq (${CSS_SGI_PLATFORM_VARIANT}, 2) +GICV3_IMPL_GIC600_MULTICHIP := 1 +endif + include plat/arm/css/sgi/sgi-common.mk RDN2_BASE = plat/arm/board/rdn2 @@ -39,6 +57,13 @@ BL1_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c BL2_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c endif +ifeq (${CSS_SGI_PLATFORM_VARIANT}, 2) +BL31_SOURCES += drivers/arm/gic/v3/gic600_multichip.c + +# Enable dynamic addition of MMAP regions in BL31 +BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC +endif + # Add the FDT_SOURCES and options for Dynamic Config FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_fw_config.dts \ ${RDN2_BASE}/fdts/${PLAT}_tb_fw_config.dts @@ -58,10 +83,3 @@ $(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config)) override CTX_INCLUDE_AARCH32_REGS := 0 override ENABLE_AMU := 1 - -RD_N2_VARIANTS := 0 1 -ifneq ($(CSS_SGI_PLATFORM_VARIANT),\ - $(filter $(CSS_SGI_PLATFORM_VARIANT),$(RD_N2_VARIANTS))) - $(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should be 0 or 1, currently set \ - to ${CSS_SGI_PLATFORM_VARIANT}.") -endif diff --git a/plat/arm/board/rdn2/rdn2_plat.c b/plat/arm/board/rdn2/rdn2_plat.c index 5bf14e3a1..8cf192972 100644 --- a/plat/arm/board/rdn2/rdn2_plat.c +++ b/plat/arm/board/rdn2/rdn2_plat.c @@ -1,12 +1,87 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include +#include +#include #include +#include #include +#if defined(IMAGE_BL31) +#if (CSS_SGI_PLATFORM_VARIANT == 2) +static const mmap_region_t rdn2mc_dynamic_mmap[] = { +#if CSS_SGI_CHIP_COUNT > 1 + ARM_MAP_SHARED_RAM_REMOTE_CHIP(1), + CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1), +#endif +#if CSS_SGI_CHIP_COUNT > 2 + ARM_MAP_SHARED_RAM_REMOTE_CHIP(2), + CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2), +#endif +#if CSS_SGI_CHIP_COUNT > 3 + ARM_MAP_SHARED_RAM_REMOTE_CHIP(3), + CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3), +#endif +}; +#endif + +#if (CSS_SGI_PLATFORM_VARIANT == 2) +static struct gic600_multichip_data rdn2mc_multichip_data __init = { + .rt_owner_base = PLAT_ARM_GICD_BASE, + .rt_owner = 0, + .chip_count = CSS_SGI_CHIP_COUNT, + .chip_addrs = { + PLAT_ARM_GICD_BASE >> 16, +#if CSS_SGI_CHIP_COUNT > 1 + (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16, +#endif +#if CSS_SGI_CHIP_COUNT > 2 + (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2)) >> 16, +#endif +#if CSS_SGI_CHIP_COUNT > 3 + (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3)) >> 16, +#endif + }, + .spi_ids = { + {32, 479}, + #if CSS_SGI_CHIP_COUNT > 1 + {0, 0}, + #endif + #if CSS_SGI_CHIP_COUNT > 2 + {0, 0}, + #endif + #if CSS_SGI_CHIP_COUNT > 3 + {0, 0}, + #endif + } +}; +#endif + +#if (CSS_SGI_PLATFORM_VARIANT == 2) +static uintptr_t rdn2mc_multichip_gicr_frames[] = { + /* Chip 0's GICR Base */ + PLAT_ARM_GICR_BASE, +#if CSS_SGI_CHIP_COUNT > 1 + /* Chip 1's GICR BASE */ + PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1), +#endif +#if CSS_SGI_CHIP_COUNT > 2 + /* Chip 2's GICR BASE */ + PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2), +#endif +#if CSS_SGI_CHIP_COUNT > 3 + /* Chip 3's GICR BASE */ + PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3), +#endif + UL(0) /* Zero Termination */ +}; +#endif +#endif /* IMAGE_BL31 */ + unsigned int plat_arm_sgi_get_platform_id(void) { return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET) @@ -25,7 +100,39 @@ unsigned int plat_arm_sgi_get_multi_chip_mode(void) SID_MULTI_CHIP_MODE_SHIFT; } +#if defined(IMAGE_BL31) void bl31_platform_setup(void) { +#if (CSS_SGI_PLATFORM_VARIANT == 2) + int ret; + unsigned int i; + + if (plat_arm_sgi_get_multi_chip_mode() == 0) { + ERROR("Chip Count is set to %u but multi-chip mode is not " + "enabled\n", CSS_SGI_CHIP_COUNT); + panic(); + } else { + INFO("Enabling multi-chip support for RD-N2 variant\n"); + + for (i = 0; i < ARRAY_SIZE(rdn2mc_dynamic_mmap); i++) { + ret = mmap_add_dynamic_region( + rdn2mc_dynamic_mmap[i].base_pa, + rdn2mc_dynamic_mmap[i].base_va, + rdn2mc_dynamic_mmap[i].size, + rdn2mc_dynamic_mmap[i].attr); + if (ret != 0) { + ERROR("Failed to add dynamic mmap entry for" + " i: %d " "(ret=%d)\n", i, ret); + panic(); + } + } + + plat_arm_override_gicr_frames( + rdn2mc_multichip_gicr_frames); + gic600_multichip_init(&rdn2mc_multichip_data); + } +#endif + sgi_bl31_common_platform_setup(); } +#endif /* IMAGE_BL31 */ diff --git a/plat/arm/board/rdn2/rdn2_security.c b/plat/arm/board/rdn2/rdn2_security.c index 9568b60cd..dff6a19e0 100644 --- a/plat/arm/board/rdn2/rdn2_security.c +++ b/plat/arm/board/rdn2/rdn2_security.c @@ -1,25 +1,63 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include #include #include - static const arm_tzc_regions_info_t tzc_regions[] = { ARM_TZC_REGIONS_DEF, {} }; +#if (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1) +static const arm_tzc_regions_info_t tzc_regions_mc[][CSS_SGI_CHIP_COUNT - 1] = { + { + /* TZC memory regions for second chip */ + SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1), + {} + }, +#if CSS_SGI_CHIP_COUNT > 2 + { + /* TZC memory regions for third chip */ + SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2), + {} + }, +#endif +#if CSS_SGI_CHIP_COUNT > 3 + { + /* TZC memory regions for fourth chip */ + SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3), + {} + }, +#endif +}; +#endif /* CSS_SGI_PLATFORM_VARIANT && CSS_SGI_CHIP_COUNT */ + /* Initialize the secure environment */ void plat_arm_security_setup(void) { + unsigned int i; - int i; + INFO("Configuring TrustZone Controller for Chip 0\n"); - for (i = 0; i < TZC400_COUNT; i++) + for (i = 0; i < TZC400_COUNT; i++) { arm_tzc400_setup(TZC400_BASE(i), tzc_regions); + } +#if (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1) + unsigned int j; + + for (i = 1; i < CSS_SGI_CHIP_COUNT; i++) { + INFO("Configuring TrustZone Controller for Chip %u\n", i); + + for (j = 0; j < TZC400_COUNT; j++) { + arm_tzc400_setup(CSS_SGI_REMOTE_CHIP_MEM_OFFSET(i) + + TZC400_BASE(j), tzc_regions_mc[i-1]); + } + } +#endif } diff --git a/plat/arm/board/rdn2/rdn2_topology.c b/plat/arm/board/rdn2/rdn2_topology.c index cad6c3704..89300f882 100644 --- a/plat/arm/board/rdn2/rdn2_topology.c +++ b/plat/arm/board/rdn2/rdn2_topology.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,20 +11,24 @@ * The power domain tree descriptor. ******************************************************************************/ const unsigned char rd_n2_pd_tree_desc[] = { - PLAT_ARM_CLUSTER_COUNT, + (PLAT_ARM_CLUSTER_COUNT) * (CSS_SGI_CHIP_COUNT), CSS_SGI_MAX_CPUS_PER_CLUSTER, CSS_SGI_MAX_CPUS_PER_CLUSTER, CSS_SGI_MAX_CPUS_PER_CLUSTER, CSS_SGI_MAX_CPUS_PER_CLUSTER, +#if (CSS_SGI_PLATFORM_VARIANT != 2 || (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1)) CSS_SGI_MAX_CPUS_PER_CLUSTER, CSS_SGI_MAX_CPUS_PER_CLUSTER, CSS_SGI_MAX_CPUS_PER_CLUSTER, CSS_SGI_MAX_CPUS_PER_CLUSTER, -#if (CSS_SGI_PLATFORM_VARIANT == 0) +#endif +#if (CSS_SGI_PLATFORM_VARIANT == 0 || (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 2)) CSS_SGI_MAX_CPUS_PER_CLUSTER, CSS_SGI_MAX_CPUS_PER_CLUSTER, CSS_SGI_MAX_CPUS_PER_CLUSTER, CSS_SGI_MAX_CPUS_PER_CLUSTER, +#endif +#if (CSS_SGI_PLATFORM_VARIANT == 0 || (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 3)) CSS_SGI_MAX_CPUS_PER_CLUSTER, CSS_SGI_MAX_CPUS_PER_CLUSTER, CSS_SGI_MAX_CPUS_PER_CLUSTER, @@ -44,6 +48,32 @@ const unsigned char *plat_get_power_domain_tree_desc(void) * The array mapping platform core position (implemented by plat_my_core_pos()) * to the SCMI power domain ID implemented by SCP. ******************************************************************************/ +#if (CSS_SGI_PLATFORM_VARIANT == 2) +const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = { + (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)), + (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)), + (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)), + (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)), +#if (CSS_SGI_CHIP_COUNT > 1) + (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)), + (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)), + (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)), + (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)), +#endif +#if (CSS_SGI_CHIP_COUNT > 2) + (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x0)), + (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x1)), + (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x2)), + (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x3)), +#endif +#if (CSS_SGI_CHIP_COUNT > 3) + (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x0)), + (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x1)), + (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x2)), + (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x3)), +#endif +}; +#else const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = { (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)), (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)), @@ -64,3 +94,4 @@ const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = { (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)), #endif }; +#endif diff --git a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h index bebc59722..639b687f1 100644 --- a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h +++ b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h @@ -92,6 +92,12 @@ SOC_MEMCNTRL_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) +#define SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(n) \ + MAP_REGION_FLAT( \ + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + SOC_MEMCNTRL_BASE, \ + SOC_MEMCNTRL_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + /* * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs. */ diff --git a/plat/arm/css/sgi/sgi_plat_v2.c b/plat/arm/css/sgi/sgi_plat_v2.c index 131cdf2b5..1a2a96629 100644 --- a/plat/arm/css/sgi/sgi_plat_v2.c +++ b/plat/arm/css/sgi/sgi_plat_v2.c @@ -42,6 +42,15 @@ const mmap_region_t plat_arm_mmap[] = { SOC_PLATFORM_PERIPH_MAP_DEVICE, SOC_SYSTEM_PERIPH_MAP_DEVICE, ARM_MAP_NS_DRAM1, +#if CSS_SGI_CHIP_COUNT > 1 + SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(1), +#endif +#if CSS_SGI_CHIP_COUNT > 2 + SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(2), +#endif +#if CSS_SGI_CHIP_COUNT > 3 + SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(3), +#endif #if ARM_BL31_IN_DRAM ARM_MAP_BL31_SEC_DRAM, #endif