Merge "feat(st): update the security based on new compatible" into integration
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commit
0e38ff2ac6
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@ -1837,11 +1837,6 @@ int stm32mp1_clk_init(void)
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return -FDT_ERR_NOTFOUND;
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}
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/* Check status field to disable security */
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if (!fdt_get_rcc_secure_status()) {
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mmio_write_32(rcc_base + RCC_TZCR, 0);
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}
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ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB,
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clksrc);
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if (ret < 0) {
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@ -2358,6 +2353,12 @@ static const struct clk_ops stm32mp_clk_ops = {
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int stm32mp1_clk_probe(void)
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{
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#if defined(IMAGE_BL32)
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if (!fdt_get_rcc_secure_state()) {
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mmio_write_32(stm32mp_rcc_base() + RCC_TZCR, 0U);
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}
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#endif
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stm32mp1_osc_init();
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sync_earlyboot_clocks_state();
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@ -250,24 +250,22 @@ const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp)
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}
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/*
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* Get the secure status for rcc node in device tree.
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* @return: true if rcc is available from secure world, false if not.
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* Get the secure state for rcc node in device tree.
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* @return: true if rcc is configured for secure world access, false if not.
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*/
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bool fdt_get_rcc_secure_status(void)
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bool fdt_get_rcc_secure_state(void)
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{
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int node;
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void *fdt;
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if (fdt_get_address(&fdt) == 0) {
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return false;
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}
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node = fdt_get_rcc_node(fdt);
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if (node < 0) {
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if (fdt_node_offset_by_compatible(fdt, -1, DT_RCC_SEC_CLK_COMPAT) < 0) {
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return false;
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}
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return !!(fdt_get_status(node) & DT_SECURE);
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return true;
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}
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/*
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@ -23,7 +23,7 @@ int fdt_rcc_read_uint32_array(const char *prop_name, uint32_t count,
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uint32_t *array);
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int fdt_rcc_subnode_offset(const char *name);
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const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp);
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bool fdt_get_rcc_secure_status(void);
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bool fdt_get_rcc_secure_state(void);
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int fdt_get_clock_id(int node);
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unsigned long fdt_get_uart_clock_freq(uintptr_t instance);
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@ -492,5 +492,6 @@ static inline uint32_t tamp_bkpr(uint32_t idx)
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#define DT_NVMEM_LAYOUT_COMPAT "st,stm32-nvmem-layout"
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#define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
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#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
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#define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure"
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#endif /* STM32MP1_DEF_H */
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