diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h index 27968409e..143385d25 100644 --- a/plat/xilinx/zynqmp/include/platform_def.h +++ b/plat/xilinx/zynqmp/include/platform_def.h @@ -36,7 +36,7 @@ * little space for growth. */ #ifndef ZYNQMP_ATF_MEM_BASE -#if !DEBUG && defined(SPD_none) +#if !DEBUG && defined(SPD_none) && !SDEI_SUPPORT # define BL31_BASE 0xfffea000 # define BL31_LIMIT 0xffffffff #else @@ -91,6 +91,13 @@ #define CACHE_WRITEBACK_SHIFT 6 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) +#define ZYNQMP_SDEI_SGI_PRIVATE U(8) + +/* Platform macros to support exception handling framework */ +#define PLAT_PRI_BITS U(3) +#define PLAT_SDEI_CRITICAL_PRI 0x10 +#define PLAT_SDEI_NORMAL_PRI 0x20 + #define PLAT_ARM_GICD_BASE BASE_GICD_BASE #define PLAT_ARM_GICC_BASE BASE_GICC_BASE /* @@ -102,8 +109,6 @@ #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_EDGE), \ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ @@ -124,8 +129,6 @@ GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_EDGE), \ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ @@ -142,6 +145,8 @@ GIC_INTR_CFG_EDGE) #endif -#define PLAT_ARM_G0_IRQ_PROPS(grp) +#define PLAT_ARM_G0_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \ + GIC_INTR_CFG_EDGE) #endif /* PLATFORM_DEF_H */ diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk index 99a4beb32..5e6915168 100644 --- a/plat/xilinx/zynqmp/platform.mk +++ b/plat/xilinx/zynqmp/platform.mk @@ -14,6 +14,8 @@ override RESET_TO_BL31 := 1 override GICV2_G0_FOR_EL3 := 1 override WARMBOOT_ENABLE_DCACHE_EARLY := 1 +EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT) + # Do not enable SVE ENABLE_SVE_FOR_NS := 0 @@ -107,6 +109,11 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ plat/xilinx/zynqmp/pm_service/pm_api_clock.c \ plat/xilinx/zynqmp/pm_service/pm_client.c +ifeq (${SDEI_SUPPORT},1) +BL31_SOURCES += plat/xilinx/zynqmp/zynqmp_ehf.c \ + plat/xilinx/zynqmp/zynqmp_sdei.c +endif + BL31_CPPFLAGS += -fno-jump-tables ifneq (${RESET_TO_BL31},1) diff --git a/plat/xilinx/zynqmp/zynqmp_ehf.c b/plat/xilinx/zynqmp/zynqmp_ehf.c new file mode 100644 index 000000000..fbf1ed04b --- /dev/null +++ b/plat/xilinx/zynqmp/zynqmp_ehf.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) Siemens AG, 2020-2021 + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +/* + * Enumeration of priority levels on ARM platforms. + */ +ehf_pri_desc_t zynqmp_exceptions[] = { + /* Critical priority SDEI */ + EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_CRITICAL_PRI), + + /* Normal priority SDEI */ + EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_NORMAL_PRI), +}; + +/* Plug in ARM exceptions to Exception Handling Framework. */ +EHF_REGISTER_PRIORITIES(zynqmp_exceptions, ARRAY_SIZE(zynqmp_exceptions), PLAT_PRI_BITS); diff --git a/plat/xilinx/zynqmp/zynqmp_sdei.c b/plat/xilinx/zynqmp/zynqmp_sdei.c new file mode 100644 index 000000000..7e92b58b6 --- /dev/null +++ b/plat/xilinx/zynqmp/zynqmp_sdei.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) Siemens AG, 2020-2021 + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* SDEI configuration for ARM platforms */ + +#include +#include +#include + +#include +#include + +int arm_validate_ns_entrypoint(uintptr_t entrypoint) +{ + return (entrypoint < BL31_BASE || entrypoint > BL31_LIMIT) ? 0 : -1; +} + +/* Private event mappings */ +static sdei_ev_map_t zynqmp_sdei_private[] = { + SDEI_DEFINE_EVENT_0(ZYNQMP_SDEI_SGI_PRIVATE), +}; + +/* Shared event mappings */ +static sdei_ev_map_t zynqmp_sdei_shared[] = { +}; + +void plat_sdei_setup(void) +{ + INFO("SDEI platform setup\n"); +} + +/* Export ARM SDEI events */ +REGISTER_SDEI_MAP(zynqmp_sdei_private, zynqmp_sdei_shared);