From 0f3a1221093256999af5f2a80e9b3d7231b9f5fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Tue, 12 Oct 2021 14:53:25 +0200 Subject: [PATCH] fix(drivers/marvell/comphy-3700): configure phy selector also for PCIe MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mvebu_a3700_comphy_pcie_power_on() function does not configure the PHY selector explicitly, it relies on the register default value. Configure the PHY selector just in case someone changed the default value. Signed-off-by: Pali Rohár Change-Id: I54048b4bb7a5eced36f7fe6592ebe108f978fff0 --- drivers/marvell/comphy/phy-comphy-3700.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c index 0ad14a800..a3e414c4b 100644 --- a/drivers/marvell/comphy/phy-comphy-3700.c +++ b/drivers/marvell/comphy/phy-comphy-3700.c @@ -815,6 +815,12 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index, debug_enter(); + /* Configure phy selector for PCIe */ + ret = mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); + if (ret) { + return ret; + } + /* 1. Enable max PLL. */ reg_set16(LANE_CFG1_ADDR(PCIE) + COMPHY_SD_ADDR, USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN);