Cortex-A57: Implement workaround for erratum 814670
Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent
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@ -125,6 +125,9 @@ For Cortex-A57, the following errata build flags are defined :
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- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision r0p0 of the CPU.
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- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision r0p0 of the CPU.
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- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
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@ -45,6 +45,7 @@
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#define CORTEX_A57_CPUACTLR p15, 0, c15
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#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)
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#define CORTEX_A57_CPUACTLR_DIS_DMB_NULLIFICATION (ULL(1) << 58)
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#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55)
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#define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
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#define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52)
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@ -45,6 +45,7 @@
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#define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0
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#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION (ULL(1) << 58)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55)
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#define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -123,6 +123,35 @@ func check_errata_813420
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b cpu_rev_var_ls
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endfunc check_errata_813420
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #814670.
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* This applies only to revision r0p0 of Cortex A57.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ---------------------------------------------------
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*/
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func errata_a57_814670_wa
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/*
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* Compare r0 against revision r0p0
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*/
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mov r2, lr
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bl check_errata_814670
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
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orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_DMB_NULLIFICATION
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stcopr16 r0, r1, CORTEX_A57_CPUACTLR
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isb
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1:
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bx r2
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endfunc errata_a57_814670_wa
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func check_errata_814670
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mov r1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_814670
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/* --------------------------------------------------------------------
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* Disable the over-read from the LDNP instruction.
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*
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@ -366,6 +395,11 @@ func cortex_a57_reset_func
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bl errata_a57_813420_wa
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#endif
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#if ERRATA_A57_814670
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mov r0, r4
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bl errata_a57_814670_wa
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#endif
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#if A57_DISABLE_NON_TEMPORAL_HINT
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mov r0, r4
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bl a57_disable_ldnp_overread
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@ -533,6 +567,7 @@ func cortex_a57_errata_report
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report_errata ERRATA_A57_806969, cortex_a57, 806969
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report_errata ERRATA_A57_813419, cortex_a57, 813419
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report_errata ERRATA_A57_813420, cortex_a57, 813420
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report_errata ERRATA_A57_814670, cortex_a57, 814670
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report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \
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disable_ldnp_overread
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report_errata ERRATA_A57_826974, cortex_a57, 826974
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -132,6 +132,34 @@ func check_errata_813420
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b cpu_rev_var_ls
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endfunc check_errata_813420
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #814670.
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* This applies only to revision r0p0 of Cortex A57.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* ---------------------------------------------------
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*/
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func errata_a57_814670_wa
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/*
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* Compare x0 against revision r0p0
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*/
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mov x17, x30
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bl check_errata_814670
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cbz x0, 1f
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mrs x1, CORTEX_A57_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION
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msr CORTEX_A57_CPUACTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a57_814670_wa
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func check_errata_814670
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_814670
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/* --------------------------------------------------------------------
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* Disable the over-read from the LDNP instruction.
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*
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@ -366,6 +394,11 @@ func cortex_a57_reset_func
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bl errata_a57_813420_wa
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#endif
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#if ERRATA_A57_814670
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mov x0, x18
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bl errata_a57_814670_wa
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#endif
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#if A57_DISABLE_NON_TEMPORAL_HINT
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mov x0, x18
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bl a57_disable_ldnp_overread
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@ -537,6 +570,7 @@ func cortex_a57_errata_report
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report_errata ERRATA_A57_806969, cortex_a57, 806969
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report_errata ERRATA_A57_813419, cortex_a57, 813419
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report_errata ERRATA_A57_813420, cortex_a57, 813420
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report_errata ERRATA_A57_814670, cortex_a57, 814670
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report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \
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disable_ldnp_overread
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report_errata ERRATA_A57_826974, cortex_a57, 826974
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@ -111,6 +111,10 @@ ERRATA_A57_813419 ?=0
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# only to revision r0p0 of the Cortex A57 cpu.
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ERRATA_A57_813420 ?=0
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# Flag to apply erratum 814670 workaround during reset. This erratum applies
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# only to revision r0p0 of the Cortex A57 cpu.
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ERRATA_A57_814670 ?=0
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# Flag to apply erratum 826974 workaround during reset. This erratum applies
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# only to revision <= r1p1 of the Cortex A57 cpu.
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ERRATA_A57_826974 ?=0
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@ -200,6 +204,10 @@ $(eval $(call add_define,ERRATA_A57_813419))
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$(eval $(call assert_boolean,ERRATA_A57_813420))
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$(eval $(call add_define,ERRATA_A57_813420))
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# Process ERRATA_A57_814670 flag
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$(eval $(call assert_boolean,ERRATA_A57_814670))
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$(eval $(call add_define,ERRATA_A57_814670))
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# Process ERRATA_A57_826974 flag
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$(eval $(call assert_boolean,ERRATA_A57_826974))
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$(eval $(call add_define,ERRATA_A57_826974))
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