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Merge pull request #1249 from masahir0y/uniphier 

uniphier: fix and improve memory layout
This commit is contained in:
davidcunado-arm 2018-02-02 22:59:16 +00:00 committed by GitHub
parent 9c00555ba6 4f557c77f5
commit 10787b0519
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 39 additions and 28 deletions
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23
plat/socionext/uniphier/include/platform_def.h
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@ -9,6 +9,7 @@
#include <common_def.h>
#include <tbbr/tbbr_img_def.h>
#include <utils_def.h>
#define PLATFORM_STACK_SIZE 0x1000
@ -27,26 +28,28 @@
#define PLAT_MAX_OFF_STATE 2
#define PLAT_MAX_RET_STATE 1
#define UNIPHIER_SEC_DRAM_BASE 0x80000000
#define UNIPHIER_SEC_DRAM_LIMIT 0x82000000
#define BL2_BASE ULL(0x80000000)
#define BL2_LIMIT ULL(0x80080000)
/* 0x80080000-0x81000000: reserved for DSP */
#define UNIPHIER_SEC_DRAM_BASE 0x81000000ULL
#define UNIPHIER_SEC_DRAM_LIMIT 0x82000000ULL
#define UNIPHIER_SEC_DRAM_SIZE ((UNIPHIER_SEC_DRAM_LIMIT) - \
(UNIPHIER_SEC_DRAM_BASE))
#define BL2_BASE (UNIPHIER_SEC_DRAM_BASE)
#define BL2_LIMIT ((BL2_BASE) + 0x00020000)
#define BL31_BASE ULL(0x81000000)
#define BL31_LIMIT ULL(0x81080000)
#define BL31_BASE (BL2_LIMIT)
#define BL31_LIMIT ((BL31_BASE) + 0x00080000)
#define BL32_BASE (BL31_LIMIT)
#define BL32_LIMIT (UNIPHIER_SEC_DRAM_LIMIT)
#define BL32_BASE ULL(0x81080000)
#define BL32_LIMIT ULL(0x81180000)
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_XLAT_TABLES_DYNAMIC 1
#define MAX_XLAT_TABLES 7
#define MAX_MMAP_REGIONS 6
#define MAX_MMAP_REGIONS 7
#define MAX_IO_HANDLES 2
#define MAX_IO_DEVICES 2

9
plat/socionext/uniphier/uniphier_bl2_setup.c
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@ -15,6 +15,9 @@
#include "uniphier.h"
#define BL2_END (unsigned long)(&__BL2_END__)
#define BL2_SIZE ((BL2_END) - (BL2_BASE))
static int uniphier_bl2_kick_scp;
void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
@ -24,6 +27,9 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
}
static const struct mmap_region uniphier_bl2_mmap[] = {
/* for BL31, BL32 */
MAP_REGION_FLAT(UNIPHIER_SEC_DRAM_BASE, UNIPHIER_SEC_DRAM_SIZE,
MT_MEMORY | MT_RW | MT_SECURE),
/* for SCP, BL33 */
MAP_REGION_FLAT(UNIPHIER_NS_DRAM_BASE, UNIPHIER_NS_DRAM_SIZE,
MT_MEMORY | MT_RW | MT_NS),
@ -36,8 +42,7 @@ void bl2_el3_plat_arch_setup(void)
int skip_scp = 0;
int ret;
uniphier_mmap_setup(UNIPHIER_SEC_DRAM_BASE, UNIPHIER_SEC_DRAM_SIZE,
uniphier_bl2_mmap);
uniphier_mmap_setup(BL2_BASE, BL2_SIZE, uniphier_bl2_mmap);
enable_mmu_el3(0);
soc = uniphier_get_soc_id();

19
plat/socionext/uniphier/uniphier_io_storage.c
View File

@ -18,8 +18,11 @@
#include "uniphier.h"
#define UNIPHIER_ROM_REGION_BASE 0x00000000
#define UNIPHIER_ROM_REGION_SIZE 0x10000000
#define UNIPHIER_ROM_REGION_BASE 0x00000000ULL
#define UNIPHIER_ROM_REGION_SIZE 0x10000000ULL
#define UNIPHIER_OCM_REGION_BASE 0x30000000ULL
#define UNIPHIER_OCM_REGION_SIZE 0x00040000ULL
static const io_dev_connector_t *uniphier_fip_dev_con;
static uintptr_t uniphier_fip_dev_handle;
@ -271,6 +274,18 @@ static int uniphier_io_usb_setup(unsigned int soc_id)
if (ret)
return ret;
/*
* on-chip SRAM region: should be DEVICE attribute because the USB
* load functions provided by the ROM use this memory region as a work
* area, but do not cater to cache coherency.
*/
ret = mmap_add_dynamic_region(UNIPHIER_OCM_REGION_BASE,
UNIPHIER_OCM_REGION_BASE,
UNIPHIER_OCM_REGION_SIZE,
MT_DEVICE | MT_RW | MT_SECURE);
if (ret)
return ret;
ret = uniphier_usb_init(soc_id, &block_dev_spec);
if (ret)
return ret;

16
plat/socionext/uniphier/uniphier_xlat_setup.c
View File

@ -8,11 +8,8 @@
#include <platform_def.h>
#include <xlat_tables_v2.h>
#define UNIPHIER_OCM_REGION_BASE 0x30000000
#define UNIPHIER_OCM_REGION_SIZE 0x00040000
#define UNIPHIER_REG_REGION_BASE 0x50000000
#define UNIPHIER_REG_REGION_SIZE 0x20000000
#define UNIPHIER_REG_REGION_BASE 0x50000000ULL
#define UNIPHIER_REG_REGION_SIZE 0x20000000ULL
void uniphier_mmap_setup(uintptr_t total_base, size_t total_size,
const struct mmap_region *mmap)
@ -37,15 +34,6 @@ void uniphier_mmap_setup(uintptr_t total_base, size_t total_size,
BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
MT_DEVICE | MT_RW | MT_SECURE);
/*
* on-chip SRAM region: should be DEVICE attribute because the USB
* load functions provided by the ROM use this memory region as a work
* area, but do not cater to cache coherency.
*/
mmap_add_region(UNIPHIER_OCM_REGION_BASE, UNIPHIER_OCM_REGION_BASE,
UNIPHIER_OCM_REGION_SIZE,
MT_DEVICE | MT_RW | MT_SECURE);
/* register region */
mmap_add_region(UNIPHIER_REG_REGION_BASE, UNIPHIER_REG_REGION_BASE,
UNIPHIER_REG_REGION_SIZE,