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plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage 

Map IO WIN to CP1 and CP2 at all stages including the BLE.
Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly.
This patch allows access to CP1/CP2 internal registers at
BLE stage if CP1/CP2 are connected.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Icf9ffdf2e9e3cdc2a153429ffd914cc0005f9eca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/36939
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
This commit is contained in:
Konstantin Porotchkin 2020-09-29 11:37:12 +03:00 committed by Manish Pandey
parent 57870747e2
commit 109873cf4a
3 changed files with 14 additions and 5 deletions
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1
plat/marvell/armada/a8k/common/ble/ble.mk
View File

@ -13,6 +13,7 @@ PLAT_MARVELL = plat/marvell/armada
BLE_SOURCES += $(BLE_PATH)/ble_main.c \
$(BLE_PATH)/ble_mem.S \
drivers/delay_timer/delay_timer.c \
drivers/marvell/iob.c \
$(PLAT_MARVELL)/common/aarch64/marvell_helpers.S \
$(PLAT_MARVELL)/common/plat_delay_timer.c \
$(PLAT_MARVELL)/common/marvell_console.c

6
plat/marvell/armada/a8k/common/plat_ble_setup.c
View File

@ -720,7 +720,7 @@ static int ble_skip_current_image(void)
int ble_plat_setup(int *skip)
{
int ret;
int ret, cp;
unsigned int freq_mode;
/* Power down unused CPUs */
@ -745,6 +745,10 @@ int ble_plat_setup(int *skip)
/* Do required CP-110 setups for BLE stage */
cp110_ble_init(MVEBU_CP_REGS_BASE(0));
/* Config address for each cp other than cp0 */
for (cp = 1; cp < CP_COUNT; cp++)
update_cp110_default_win(cp);
/* Setup AVS */
ble_plat_svc_config();

12
plat/marvell/octeontx/otx2/t91/t9130/board/marvell_plat_config.c
View File

@ -46,15 +46,19 @@ int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size,
*****************************************************************************
*/
struct addr_map_win io_win_memory_map[] = {
#if (CP_COUNT > 1)
/* SB (MCi0) internal regs */
{0x00000000f4000000, 0x2000000, MCI_0_TID},
#if (CP_COUNT > 2)
/* SB (MCi1) internal regs */
{0x00000000f6000000, 0x2000000, MCI_1_TID},
#endif
#endif
#ifndef IMAGE_BLE
/* SB (MCi0) PCIe0-2 on CP1 */
{0x00000000e2000000, 0x3000000, MCI_0_TID},
/* SB (MCi1) PCIe0-2 on CP2 */
{0x00000000e5000000, 0x3000000, MCI_1_TID},
/* SB (MCi0) internal regs */
{0x00000000f4000000, 0x2000000, MCI_0_TID},
/* SB (MCi1) internal regs */
{0x00000000f6000000, 0x2000000, MCI_1_TID},
/* MCI 0 indirect window */
{MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID},
/* MCI 1 indirect window */